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12_bit_mac_unit

Final Project of EE477L

16-bit-adder-in-verilog

This project is coded in verilog and I have used four 4-bit full adders to realize the 16 bit full adder.

16-bit-binary-to-bcd-conversion---double-dabble

8-bit-sipo-shift-register-right-shift---verilog-code-smulation

This project uses verilog to model and deisgn a SIPO right shift 8-bit shift register.

arduino-digital-clock

Hey guys, hope you all are doing great. Thanks for tuning in. This time I have made a digital clock using Arduino. This is kind of those short and simple project which is doable by anyone. So Let us know your thoughts on it.

booth-s-multiplication-algorithm-in-verilog-datapath-control

Using the Datapath and Control Design approach, I made a system to calculate the GCD of two numbers. This is an example that was given in the NPTEL course 'Hardware Modeling Using Verilog' by Prof. Indranil Sengupta.

computing-gcd-of-two-numbers-using-datapath-and-control-design

Using the Datapath and Control Design approach, I made a system to calculate the GCD of two numbers.

control_ws2812b_led_by_spartan6_fpga

creating-pwm-with-vriable-signal-width-in-xilinx-spartan-6

In this project I created PWM signal out of an FPGA (Xilinx Spartan 6), in which the PWM width can be altered with a push of button. That means we can create duty cycle 0 to 100 percent ideally.

detect-sequence-0110-with-overlap-using-verilog

Detect the sequence 0110 in a bit stream and put an output high.

digital-clock-in-spartan-6-fpga

Digital Clock coded in Verilog. Simulated in iverilog. Implemented on Xilinx Spartan 6 FPGA and seven segment display.

diy-arduino-uno

Hey guys, Thanks for tuning in. This time, I will show you how you can build your own Arduino Uno board at home. This is super handy and cost-effective also. With that, you can modify the board to your needs as I have done here. The process is very straightforward and I will guide you through this process in detail. So let's start making our own Arduino board.

final-project-anushkapoojary

final-project-anushkapoojary created by GitHub Classroom

flip-flop-in-fpga-verilog

flip-flop-models-in-verilog

D, JK, T, RS flip flops modelled and simulated in verilog

four-bit-up-counter-in-verilog---fpga

how-ws2812b-led-strip-works-and-controlling-with-verilog

In this project we will control a WS2812B LED strip using Spartan 6 FPGA and Verilog.

icl7107-voltmeter

In this video I have made a super simple to use digital voltmeter that can measure voltages from 20 mV to 200V. The voltmeter can be charged once it's out of power. In one cycle the battery can run this circuit for 12 hours. Hope you will like this project.

ir-relay-home-automation

In this project I will show you how to switch on/off AC appliances with any IR remote. This system will also have a timer function inbuilt so that you can set a timer on or timer off to switch your device automatically. Hope you will like this. Thanks :)

mealy-macine-fsm-detect-101010

In this project we are detecting the sequence '101010' with possible overlapping. The image below is the simulation result. Coded in Verilog.

nano-binary-clock

Hey guys, In this project I have showed how you can make a DIY binary clock with arduino. Most of the binary clocks don't have seconds, because of the limited number of I/O ports available in arduino. But in this project I have make this clock to show us the time in HH : MM : SS format with the help of 20 leds. The interesting fact is that I used only 5 pins from arduino to make this happen. This concept is called charlieplexing. Previously I have uploaded a video on this topic. If you don't know about it then do watch it and then start from here.

opcode-generator-for-mips32-risc-processor

This python script will help you to get the machine code of corresponding op-code for MIPS 32 RISC processor. Look into the other repository about modeling this particular processor in verilog. Not all instructions are enabled here. However, you can add other instructions to the json file and modify the code accordingly.

pwm-generator-in-verilog

Verilog code to generate pwm signal

shift-and-add-three---convert-binary-to-bcd

Using the popular shift and add three algorithm, which is also known as double dabble, I converted binary number to BCD.

shift-register-vhdl

This is a simple Serial In Parallel out shift register written in VHDL.

system-verilog-basics

This repo is not about any projects. It's just about why Systemverilog is better than Verilog and it's features.

tic-tac-toe-python

This is a 2 player tic-tac-toe game designed in python3.5.

travelling-trojan

final-project-Zzixin created by GitHub Classroom

xilinx-mealy-machine-assignment

This project is implemented and simulated Iverilog and plotted by GTKwave. Problem statement is following - Design a sequence detector implementing a Mealy state machine using three always blocks. The Mealy state machine has one input (ain) and one output (yout). The output yout is 1 if and only if the total number of 1s received is divisible by 3 (hint: 0 is inclusive, however, reset cycle(s) do not count as 0- see in simulation waveform time=400). Develop a test bench and verify the model through a behavioral simulation. Use SW0 as the clock input, SW1 as the ain input, the BTNU button as reset input to the circuit, number of 1s count on LED7:LED4, and LED0 as the yout output. Go through the design flow, generate the bitstream, and download it into the Nexys3 board. Verify the functionality.