suhasr1991 Goto Github PK

followers: 5.0 following: 0.0 repos: 4.0 gists: 0.0

Name: Suhas Sunil Raut

Type: User

Company: @cisco

Location: San Jose, California, USA

Blog: www.linkedin.com/in/suhassraut

Suhas Sunil Raut's Projects

5-stage-pipelined-ieee-single-precision-floating-point-adder-design

In this project a 32 bit Floating point adder was designed using Verilog HDL. This design was pipelined to reduce the computations in a single cycle.

can-bus-controller-design

CAN Bus controller was designed for standard data frame and remote data frame. Bit stuffing was implemented to ensure that for every 5 consecutive same bits an inverted bit was inserted in the frame. Cyclic Redundancy Code(CRC) was implemented for error handling. Bit timing state machine was implemented to achieve greater synchronization at the receiver. AHB protocol (slave/master) was implemented to receive and transmit the data bit at a time on the bus. Further 8 AHB-CAN Transmitter were instantiated and operated over the bus. These devices used a round robin arbitrator to get the data on bus towards test bench(or other devices).

convolutional-neural-network-hardware-using-verilog

A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers. Sigmoid case statement was also implemented in verilog to get the sigmoid values for intermediate outputs in a layer. This design was simulated and synthesized at 50 MHz on Quartus Prime 17.0. The FPGA family was Cyclone V. Total logic elements used were 724, total bits used 121856(only 50% use of memory).

veriification-of-lcd-controller-design

A project on UVM to verify the functionality of LCD controller design. A UVM testbench was created from scratch. AHB master/slave agents created to get the data in memory for LCD controller to access the data. Monitors and scoreboards were created to compare the data from LCDVD output to expected output in a file. Also wrote a logic to compare the number of cycles between two frame pulses with the expected number of cycles in a file. This was done such that the frame is received in the two frame pulses.

suhasr1991 Goto Github PK

Suhas Sunil Raut's Projects

5-stage-pipelined-ieee-single-precision-floating-point-adder-design

can-bus-controller-design

convolutional-neural-network-hardware-using-verilog

veriification-of-lcd-controller-design

Recommend Projects

React

Vue.js

Typescript

TensorFlow

Django

Laravel

D3

Recommend Topics

javascript

web

server

Machine learning

Visualization

Game

Recommend Org

Facebook

Microsoft

Google

Alibaba

D3

Tencent