Comments (3)
If we read this correctly, you’ve made an SCR1 configuration without SCR1_BRKM_EN and want to exclude the riscv-compliance "breakpoint" test from the list for simulation using Verilator (please, confirm).
Unfortunately, we don’t think the proposed method will work as Verilator does not support all simulation features of the SystemVerilog language at the moment, in particular, the comparison of two strings. You could read more about supported features in the "Verilator manual" here: https://www.veripool.org/projects/verilator/wiki/Documentation
As a possible solution, we suggest to manually exclude this test from the list. To do this, please edit the file ./sim/tests/riscv_compliance/Makefile by adding a new line to it
cut_list += breakpoint
As a reference - the same was done for several incompatible riscv-compliance tests here:
scr1/sim/tests/riscv_compliance/Makefile
Line 71 in 9bc6cbb
Best regards,
Kate
from scr1.
Actually, I used ncsim, vcs & modelsim for simulation. Apparently, the method I proposed works in these simulators except Verilator. Put the test in the cut list is the easiest way. However, the situation may need to be addressed in README or document to remind users.
from scr1.
Thank you for your comment. We will definitely include such a description in the next README and UM release.
from scr1.
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from scr1.