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aiffel-quest

이태훈 (AIFFEL)

aiffel_0

study

aiffel_online5

손정민_AIFFEL_온라인5기

aiffel_online_5th

최철웅(AIFFEL)

aiffel_quest

aiffel_quest_rep

chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

computervision

딥러닝과 컴퓨터비전 - 고려사이버대학교 이홍섭

cosmos-plus-openssd

Cosmos OpenSSD + Hardware and Software source distribution

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

deep-learning-with-python-2nd

<케라스 창시자에게 배우는 딥러닝 2판> 도서의 코드 저장소

deep-learning-with-tensorflow

Deep Learning with TensorFlow by Packt

deep-learning-with-tensorflow-second-edition

Deep Learning with TensorFlow – Second Edition, published by Packt

deep_learning_blocks

DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.

deep_learning_routines

DLR: High-Level Synthesizable Deep Learning Routines with Python/PyTorch Interfaces

deeplearningzerotoall

TensorFlow Basic Tutorial Labs

first-repository

first_rep

hard-cv

A repository of IPs for hardware computer vision (FPGA)

heimann-htpa-api

REST API that handle the driver of HTPA 32x32 thermophile array sensor [https://www.heimannsensor.com/32x32] for NVIDIA Jetson Xavier. As the driver and framework was implemented entirely in Python, it easily can be moved to other SBC(Single board computer) platforms. There are two endpoints that return raw data(before temperature interpolation) and temperature data. In case of temperature data calibration must be done to get accurate results, for while all these calibrations values are hard-coded.

learnaiwithexcel

<엑셀로 배우는 인공지능> 리포지토리

lm32

LatticeMico32 soft processor

mipi_csi_receiver_fpga

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy Version!

netfpga-sume-public

NetFPGA-SUME public repository

openisp

Image Signal Processor

orpsoc-de0_nano

ORPSoC rev 1 fork (from git://openrisc.net/stefan/orpsoc) for de0_nano board with custom made expansion board

pandas_exercises

Practice your pandas skills!

pipecnn

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

pulpino

An open-source microcontroller system based on RISC-V

standalone-deeplearning

2019 KAIST 딥러닝 홀로서기 세미나용 저장소입니다.