Comments (5)
Hi Akshay,
Which FPGA are you using?
Loading overlay requires a .bit file and a .hwh or .tcl file with the same filename at the same location.
For example, SkyNet.bit and SkyNet.hwh, or SkyNet.tcl.
The required .hwh and .tcl varies with the FPGA you are using.
Regards,
Cong
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Hi Cong,
I am using the Ultra96 board with following features.
• Zynq UltraScale+ MPSoC ZU3EG A484
• 1GByte (256M x32) LPDDR4 Memory
• MicroSD Socket
• Wi-Fi / Bluetooth
• DisplayPort
• 1x USB 3.0 Type Micro-B upstream port
• 2x USB 3.0 Type A downstream ports
• 40-pin Low-speed expansion header
• 60-pin High speed expansion header
• 85mm x 54mm form factor
• Linaro 96Boards Consumer Edition compatible
from skynet.
Ultra96 requires the .hwh file.
Do you have a SkyNet.hwh under the direction of "//mnt//Deploy//"?
Best,
Cong
from skynet.
Yes, SkyNet.hwh is present in "//mnt//Deploy//" directory.
The error is regarding a .tcl file, and there is no .tcl file in the /Deploy directory.
Thanks,
Akshay
from skynet.
Sorry for late reply. In Ultra96 a .hwh file is first required instead of .tcl file; .tcl is required only when a .hwh is not found.
Can you try to put the whole design in another dictionary (not under //mnt)? Maybe under somewhere like /xilinx/jupyter
Best,
Cong
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