Comments (6)
Code is now publicly available. I did make own repository, hopefully you don't mind.
https://github.com/ekknod/pcileech-wifi/
- minimal BAR support
- wifi card "emulation"
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This is very nice, I'll take a good look once I'm back home from vacation (in a weeks time). I'm sure this will be useful for quite a few others 👍
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You could use the leechcorepyc python library to see any TLPs received if set up properly https://github.com/ufrisk/LeechCore/wiki/LeechCore_API_Python
MWr is a posted TLP (i.e. no reply is required) so those would always "succeed" if implementing a dummy BAR.
As for the MRd I suspect there may be an alignment issue. Make sure the CplD TLP sent in response to a MRd never crosses a 0x80 boundary. If it does you may have to fragment it into two CplD responses.
I have some thoughts about implementing this in software (but it will be much slower than doing it on the FPGA), maybe much too slow, but it would also be easier to customize responses for research purposes.
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I have added AMD support now to wifi project. I decided to change approach to PIO module (provided by xilinx).
Seems to work okay. I changed your Multiplexer little bit to support PIO. I bet it could be implemented better as well.
https://github.com/ekknod/pcileech-wifi/blob/main/src/pcileech_pcie_tlp_a7.sv#L111
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This is some super awesome news 👍 Project completed then I guess?
Having full support (at least for smaller BARs) in the firmware opens up so many possibilities. And if you have some networking board emulation working it's super interesting for some research as well :)
I hope to finish up my slower API-based software implementation in the next few weeks, but it's quite boring to add support to all the different programming language APIs I provide. Also, I want to get some other changes in there as well...
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"Project completed then I guess?"
That's correct. It was minimal project, what did little bit get out of hands since needed to do more than originally was planned to. classic scenario.
"I hope to finish up my slower API-based software implementation in the next few weeks, but it's quite boring to add support to all the different programming language APIs I provide. Also, I want to get some other changes in there as well..."
Ah.. I can feel the pain. That's indeed boring and easy to make errors.
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Related Issues (20)
- Does the firmware support Kintex 7 Chips? HOT 1
- Q about TLP completion timeout HOT 1
- Xilinx PCIe parameters HOT 3
- Q on receiving data from FPGA HOT 3
- Question: Can I effectively use the Screamer PCIe Squirrel in a single PC setup. HOT 1
- 0x55556666 padding in the middle of receiving a TLP? HOT 4
- This device cannot be started. (Code 10) HOT 1
- pls help me HOT 2
- About solutions to some problems and some overlooked code. HOT 20
- Advice Request: Ported project to new board and 1Gbit Ethernet, how can I make it faster? HOT 5
- Is it possible to limit the number and frequency of TLPs that are actively sent on the software side?
- Keys HOT 1
- memory issue HOT 1
- Leetdma Abnormal speed measurement
- Leetdma Abnormal speed measurement HOT 2
- How to fix disconnect to the fpga board HOT 1
- ERROR: [Common 17-170] Error when generating project files HOT 6
- zdma ip core seems to be broken HOT 1
- MPVDMA HOT 1
- Why using 7 Series FPGAs Integrated Block for PCI Express ip core instead of others? HOT 1
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