ummidichandrika Goto Github PK

My name is UMMIDI CHANDRIKA, I am currently a Undergraduate in Electronics and Communication Engineering at Jawaharlal Nehru Technological university, Vizianagaram. I am always curious about how a square centimetre comprises millions of devices. It's quite interesting to write such codes that allow manufacturers to make efficient devices. Digital Electronics is my favourite subject, The World of 0 and 1 fascinated me

✨Technical Proficiencies Include:

🔸HDL: Verilog

🔸HVL: SystemVerilog

🔸VERIFICATION METHODOLOGY: Constraint Random Coverage Driven-Verification | Assertion Based Verification - SVA

🔸TB Methodology: UVM( Universal Verification Methodology)

🔸EDA TOOLS:Mentor Graphics-Questasim, Modelsim, Intel Quartus Prime, Xilinx ISE 14.7

🔸DOMAIN: ASIC/FPGA front-end Design and Verification

🔸Protocols : I2C, UART , SPI, APB, AHB, AXI

🔸PROGRAMMING LANGUAGES: C[Datatype Array | Pointers List Memory Allocation | Functions Queues and stacks] || C++ [Oops Concepts, Inheritance, Polymorphism, Encapsulation, Abstraction]

🔸OPERATING SYSTEMS:Linux, Windows

🔸CORE SKILLS: [RTL Coding using Synthesizable constructs of Verilog | FSM based design Simulation | CMOS Fundamentals Code Coverage | Functional Coverage |Synthesis | Static Timing Analysis | Assertion Based Verification using System Verilog Assertions]

HERE ARE MY OTHER SKILLS

MATLAB || Microsoft Office || MASM Software || Multisim || Proteus Software

This repository will act as a resume where I can show off my skills in form of projects that acts as a testament. And I will add more repositories in future to develop a great collections of things that I am into.

Projects I have worked on to build my Portfolio:

• 100DaysofRTL

• Router 1*3 RTL Design and Verification

• AHB2APB Bridge IP Core Verification

• Design of UART Protocol using Verilog

• Design and Verification of Asynchronous FIFO

  Future Projects :

  • UVM CODING from Basics to Advanced
  • PROTOCOLS