Unknown instruction in the iord group about faucon HOT 1 CLOSED

Further research and some consultance with hexkyz revealed that the instruction appears to be an iords form. There are iowr and iowrs forms, which perform asynchronous and synchronous write operations to an I/O register, respectively. For reads, there is a similar mechanism as through how the Falcon processor is designed. While iord does asynchronous reads, this newly discovered iords form performs synchronous reads. While such a distinction makes sense for write access, it doesn't for read access and so the behavior of these instructions doesn't really make a difference in practice.

The asynchronous iord form seems generally preferred over the synchronous iords form by NVIDIA's codegen backend, also in cases where the following instruction depends on the value from the MMIO, which proves the last point.

from faucon.