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amaranth

A modern hardware definition language and toolchain based on Python

bin-tree-diff

A recursive diff for toolchain refactoring equivalence testing all the way down to object files in static libraries

embeddedappsec

Embedded AppSec Best Practices

embench-iot

The main Embench repository

esphome-devices

esphome configs for my sensors

lang-talk-unbash

Slides for my talk about coping with a bashy world

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

matklad.github.io

My coding related blog

meetups

A community around PL at Prague.

microzig

Unified abstraction layer and HAL for several microcontrollers

nixpkgs

Nix Packages collection & NixOS

nmigen-gateware

An experiment for building gateware for the axiom micro / beta using nmigen and yosys

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

pandoc-minted

A pandoc filter that has the LaTeX writer use minted for typesetting code.

prettyplace

The cutest standard cell placer yet

qtrvsim

RISC-V CPU simulator for education purposes

regz

Generate zig code from ATDF or SVD files for microcontrollers.

riscv-benchmark-automation

Collection of benchmarks to run for the RISC-V architecture on Spike, with a TUI made with curses.

riscv-tests

sycl-badge

MicroZig running on the PyBadge! https://badgesim.microzig.tech/

tt-support-tools

tools used by project repos to test configuration, generate OpenLane run summaries and documentation

tt02-chase-the-beat

Chase the beat - open source silicon for TinyTapeout 2

vexbench

VexRISCV for compiler benchmarking

vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

vga-thingy

Submission template for Tiny Tapeout 7 - Verilog HDL Projects

yosys

Yosys Open SYnthesis Suite

zig

General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software.