Name: Simon Southwell
Type: User
Bio: Retired logic, s/w and systems designer, with a background in wireless/cellular and high performance computing. Now developing open-source IP for all to use.
Twitter: simon_southwell
Location: Cambridge, United Kingdom
axi4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
bmp
Command line bitmap manipulation utility
cosim
OSVVM submodule for Co-simulation features
cpu6502
A 6502 Instruction Set Simulator
cpu8051
Intel(R) 8051 Instruction Set Simulator
documentation
OSVVM Documentation
dpram
DpRam
eccexamples
Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material
ethernet
OSVVM Ethernet Library
firfilter
Verilog finite impulse response filter
jfif
JFIF and JPEG file decoder software
kernel_module
Linux Kernel Module Template
lm32fpga
FPGA development board (DE1) targetted lm32 based systems design for Verilog
mem_model
High speed C/C++ based behavioural Verilog memory model
mem_subsys
Memory sub-system component project (cache/MMU)
mico32
LatticeMico32 instruction set simulator project
osvvm
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
osvvm-common
Packages that implement OSVVM's model independent transactions and other shared verification component support packages. Required for all OSVVM verification components. AddressBusTransactionPkg - AXI, AxiLite, ... StreamTransactionPkg - AxiStream, UART, ...
osvvm-scripts
OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation
osvvmlibraries
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
pcievhost
PCIe (1.0a to 2.0) Virtual host model for verilog
pli_test
Test of VProc and mem_model PLI components in Aldec simulators
riscv
Open source ISS and logic RISC-V 32 bit project
slzw
Simple LZW codec in C
sparc
Sparc version 8 Instruction Set Simulator
spi_guyeschemann
OSVVM SPI Verification Component.
tcpippg
10GbE XGMII TCP/IPv4 packet generator for Verilog
uart
OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break errors.
usbmodel
USB virtual model in C++ for Verilog
videobus_louisadriaens
Fork of VideoBus by Louis Adriaens
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
Django
The Web framework for perfectionists with deadlines.
Laravel
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
Microsoft
Open source projects and samples from Microsoft.
Google
Google ❤️ Open Source for everyone.
Alibaba
Alibaba Open Source for everyone
D3
Data-Driven Documents codes.
Tencent
China tencent open source team.
