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chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel-testers

Provides various testers for chisel users

comba

A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications

hector

A hardware synthesis framework with multi-level paradigm

mojo

The Mojo Programming Language

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow

openroad-flow-scripts

panda-bambu

PandA-bambu public repository

polygeist

scalabooks

List of Scala books. (PDF download)

scalehls

Scalable High-Level Synthesis through MLIR

the-algorithm

Source code for Twitter's Recommendation Algorithm

treadle

Chisel/Firrtl execution engine

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

xiangshan

Open-source high-performance RISC-V processor

yosys

Yosys Open SYnthesis Suite