Block ram reads within ~36 cycles of device reset always return 0, but only on the first reset after device reconfiguration. about icestorm HOT 2 CLOSED

Forgot the relevant .pcf that maps out_debug to the LEDs on the breakout board -

set_io clk_in J3
set_io --warn-no-port out_debug[0] B5
set_io --warn-no-port out_debug[1] B4
set_io --warn-no-port out_debug[2] A2
set_io --warn-no-port out_debug[3] A1
set_io --warn-no-port out_debug[4] C5
set_io --warn-no-port out_debug[5] C4
set_io --warn-no-port out_debug[6] B3
set_io --warn-no-port out_debug[7] C3

from icestorm.

This is a hardware issue with iCE40 block rams. There is nothing the software tool-chain can do about it. You simply have to take this into consideration when creating your HDL designs.

Here is another demo for this issue:
http://svn.clifford.at/handicraft/2017/ice40bramdelay

You can synthesize this demo with Lattice iCEcube2 as well and you will observe the same issue. (But you will have to use LSE and set the "Propagate Constants" option to False, otherwise it will incorrectly optimize away the entire design. This is because the Lattice tools don't not really understand register initialization, so they think everything is undefined if there is no external reset signal.)

from icestorm.