Comments (2)
I've now fixed the performance problem in git commit 9a34486.
Note that the code you posted is not valid synthesizable code! You create BITS+1
conflicting drivers for out
here. In cases like this with N conflicting drivers and latched logic (logic loops), the opt_mux pass had a complexity of O(N!). There was no performance problem in valid synthesizable code.
I think you intended to write something like the following instead:
/* Count leading zeroes by independent prefix comparison: works for non-power-of-two sizes: */
module count_leading_zeroes (in, out);
parameter BITS = 4; /* no problem */
/* set parameter BITS = 32 or some BIG_NUMBER and watch the optimizer spinning.... */
localparam OUT_BITS = $clog2(BITS) + 1;
input [BITS-1:0] in;
output reg [OUT_BITS-1:0] out;
integer i;
always @(*) begin
for (i=0; i<BITS; i=i+1) begin
if (in[BITS-1:BITS-1-i] == { { i { 1'b0 } }, 1'b1 }) begin
out = i;
end
end
if (in == 0) begin
out = { 1'b1 , { OUT_BITS - 1 { 1'b0 } } };
end
end
endmodule
This of course still models a latched logic block (logic loop), which is generally considered bad design style. So this version of your code only fixes the issue with the conflicting drivers.
from yosys.
That's indeed correct, thank you for the quick response! Is it possible to issue a warning in this case?
from yosys.
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from yosys.