Related Issues (20)
- Yosys could not make use of the read_en signal HOT 2
- Crash when using -chparam and '0 as input to a module
- LUTs not topologically sorted after write_verilog HOT 6
- Makefile need not include the -lrt in the Windows machines LDFLAGS HOT 2
- any optimization options to disable special kind of optimization?
- write_smt2: bugs caused by the '>>' operator under certain circumstances HOT 1
- Write to the same memory in different always blocks HOT 1
- write_smt2: bugs caused by a corner case in constant propagation HOT 1
- dummy adder
- plugin Pass cannot override Pass::post_execute()
- Yosys accepts non standard delay specification
- Netlist for decoder HOT 2
- write_smt2: redundant uninterpreted function HOT 1
- -q option not reporting some errors with incorrect commands
- frontend support non-synthesizable constructs in Verilog HOT 2
- Yosys synthesis breaks CPU functionality HOT 7
- [ERROR] Synthesis RTL with unpack/pack array internal signal
- sby: mathsat failures emit python errors in yosys-smc (Python IndexError exception thrown) HOT 1
- ABC bundled with yosys-0.29 release fails to build: error: ‘intptr_t’ was not declared in this scope; did you mean ‘abc::intptr_t’? HOT 1
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