Unexpected Result from `synth_gowin` Pass about yosys HOT 4 CLOSED

I'm fairly sure this is not a bug, and the optimizer is allowed to assume that undriven nets take any value that it finds convenient.

from yosys.

I would make the argument that it is a bug from the POV of intention. If I'm not misinterpreting what setundef does, then I believe synth_gowin 'intends' to set undriven nets to 0.

In addition to that, the undriven net itself is not really being driven HIGH, only the result of the expression it is a part of. When I try to assign the undriven net to an output, that output is grounded. To demonstrate this, I added an additional output, undriven_wire_out to bug_top and assigned undriven_wire to it.

These are the final assignments to the nets per the log:

#TRACE# Connection in module bug_top: \this_sub.buggy_a = 1'1
#TRACE# Connection in module bug_top: \undriven_wire = 1'x
#TRACE# Connection in module bug_top: \undriven_wire_out = 1'x

And from the json output, I can see that:

 "undriven_wire_GND_G": {
          "hide_name": 0,
          "type": "GND",
          "parameters": {
          },
          "attributes": {
          },
          "port_directions": {
            "G": "output"
          },
          "connections": {
            "G": [ 19 ]
          }
        },
        "undriven_wire_out_OBUF_O": {
          "hide_name": 0,
          "type": "OBUF",
          "parameters": {
          },
          "attributes": {
            "keep": "00000000000000000000000000000001"
          },
          "port_directions": {
            "I": "input",
            "O": "output"
          },
          "connections": {
            "I": [ 19 ],
            "O": [ 6 ]
          }
        },

So it appears I'm ending up with a case where:

buggy_a = (a | undriven_wire) = 1'1 (undriven_wire is assumed to be 1'1)

but

undriven_wire_out = undriven_wire = 1'0 (per the json output above, `undriven wire` is grounded) 

This is consistent with the results I got from running this on an actual device, and very similar to the original challenge I encountered. Even if the optimizer makes the choice to set undriven_wire HIGH, doesn't it have to be consistent with that decision?

from yosys.

Even if the optimizer makes the choice to set undriven_wire HIGH, doesn't it have to be consistent with that decision?

Nope, each time 'x is replicated it can take a different value, similar to e.g. undef in LLVM. This is a deliberate part of its semantics.

(I agree with you that invoking this semantics whenever you forget to initialize something is undesirable. But this is how Verilog is designed. C and C++ have similarly counterintuitive issues for similar reasons. If you stick with Verilog this is what you get.)

from yosys.

That's fair enough. Even if it is certainly jarring to encounter.

Maybe it would be nice to have an option to tell synth scripts like synth_gowin to set all undriven nets to 0 prior to optimization.

Thank you very much for your time 🙏

I'll go ahead to close the issue.

from yosys.