Yosys Verilog Parsing Error: Unable to Synthesize After Reading File about yosys HOT 2 OPEN

Changing lines 31 and 32 to the following makes it compile fine:

                  reg289[(3'h6):(3'h5)] : {"Q",
                      ($unsigned((8'hb6)) ? "t" : "e")}));

Looking at the source where the assert is being raised it seems to be a problem with the parsing of string constants: // create an AST node for a constant (using a string in bit vector form as value). The git blame in that section also has the commit message "Fixed constant "cond ? string1 : string2" with strings of different size," which leads me to suspect that this is the same bug that was previously believed to be fixed. Extending the "t" string to the same length as "eLOYX7WZioxFD2iW" also fixes the problem, so that does seem to be what is happening, however swapping the order of strings such that the longer string is first also fixes the problem.

from yosys.

Minimal example (for the error):

module top ();
wire [15:0] x = {"1", "\0"};
endmodule

wire [23:0] y = {"1", 1 ? "a" : "bc"}; is closer to the example given here, combining both the problem above and the zero extension used in the ternary.

from yosys.