Vivado+Verilator and Yosys syntax inconsistency about yosys HOT 3 CLOSED

It may also be a difference in versions of SystemVerilog as you point out in the other thread.

from yosys.

I would assume that the two tools that you mentioned parse this as an empty module item, not an optional semicolon at the end of the statement. However, I don't think an empty module item is part of either Verilog or SystemVerilog.

Also: '0' is not a valid Verilog expression. The strings 0 and "0" both would be..

I thought I'd add support for empty module items and just print a warning for them, but as it turns out, at least the naive way of doing that would introduce reduce/reduce conflicts into the Yosys Verilog parser. So I'm not adding support for that..

from yosys.

First of, sorry about '0', it should just have been 0, or 1'b0 - I wrote this minimal example from a more complicated one without testing it before submitting the ticket.

I am not sure what you mean by an "empty module item". Whether or not I have a semicolon at the "end" keyword, the code works and it behaves the same in both case, hence, the phrasing optional. Just to be sure that you understood me correctly here are the two versions:

module top(A, clk, rst);
   input clk, rst;   
   output A;   

   always @(posedge clk, posedge rst) begin
      A <= 0;      
   end;  
endmodule 

vs.

module top(A, clk, rst);
   input clk, rst;   
   output A;   

   always @(posedge clk, posedge rst) begin
      A <= 0;      
   end
endmodule 

This is not a reopening of the ticket, I just wanted to make sure that I was clear enough in the first ticket.

from yosys.