Comments (4)
Printing this error is exactly the expected result for $finish
. The following example demonstrates the how it can be used:
module test(...);
parameter GPIO_COUNT = 16;
...
initial begin
if (GPIO_COUNT < 0 || GPIO_COUNT > 16) begin
$display("Parameter Error: GPIO_COUNT must be in range 0..16");
$finish;
end
end
...
endmodule
from yosys.
In your example, $finish is used as an abort command when parameters etc. are illegal. Then it makes sense to terminate the program during compiling.
In my case, $finish is used for terminating the testbench simulation. As you can see in my provided example, we only simulate 100 time units (#100 $finish;
, the other logic was omitted in the initial block). In this case $finish should only terminate during evaluation, not compilation. Does that mean I should use something else like $stop instead of $finish here?
from yosys.
I don't really understand why you are trying to synthesize your testbench. In synthesis, all #
-delays are ignored, so your example effectively contains initial $finish;
.
from yosys.
Hmm, I see your point. I imported the whole source tree by read_verilog
, which happened to include the testbench files. Afterwards I call hierarchy
to specify the top design.
I just took another look at the document, and used -defer
option in read_verilog
to avoid this problem. Thanks!
from yosys.
Related Issues (20)
- part-selects (`$shift`, `$shiftx`) create huge MUX-trees HOT 25
- How to figure out the actual name of the flipflop in yosys? HOT 4
- Improve write_verilog speed HOT 2
- ERROR: syntax error, unexpected TOK_REAL HOT 3
- During synthesis, the addition of optimization passes such as opt_clean and opt_reduce after ABC optimization has resulted in errors in register assignment. HOT 5
- The 'flatten' command adds always/if statements that weren't in the original code HOT 9
- Liberty front end doesn't properly parse boolean expressions HOT 1
- nlatch Verliog code synthesis question
- Inconsistency Issue in Synthesis and Simulation Results after Custom Synthesis Flow with fsm -norecodec and opt_expr -fine Pass in Yosys HOT 2
- SystemVerilog procedural assignments within expressions HOT 3
- Warnings for missing backticks HOT 2
- Memory overflow leading to Yosys crash
- Support for more series of anlogic FPGAs
- LEC failed after yosys synthesis HOT 2
- compile fails on abc/src/misc/extra/extraUtilUtil.c: "ISO C++17 does not allow 'register' storage class specifier" HOT 1
- compilation error at the very first with Centos 7
- Suboptimal default synthesis of `$bmux`, `$shiftx`
- Inconsistency Issue with Continuous Assignment Error after FSM Optimization using opt_dff and Other Passes HOT 4
- synthesis adder chain HOT 1
- i386 (only) test failure: Error opening grom.fst as FST file HOT 8
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from yosys.