Comments (1)
When using positional ports (i.e. S S_0 (in[31:24], out[31:24])
instead of S S_0 (.in(in[31:24]), .out(out[31:24]))
then you have to run hierarchy
before doing anything else with the design. This should always be the first command you execute after reading the design!
Before hierarchy
is run on the design you posted, it is not known to yosys which ports on cells like S_0
are inputs or outputs, thus the warnings. (The flatten
pass does also resolve positional ports, that's why flatten
works without running hierarchy
first.)
Btw: Instead of calling something like hierarchy; proc; opt_clean; ...
after reading the design you can also simply run prep
.
from yosys.
Related Issues (20)
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- ABC: execution of command failed return code 139. HOT 3
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- Yosys Optimization Issue: Process Stuck at OPT_CLEAN Pass HOT 1
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- Optimization Sequence Induces Synthesis Errors Leading to Simulation Inconsistencies HOT 10
- Optimization Sequence Leads to Functionally Incorrect Synthesis Output in Yosys HOT 1
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