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Name: Jude Zhang
Type: User
Company: Freestyle
Bio: A digital verification engineer.
Name: Jude Zhang
Type: User
Company: Freestyle
Bio: A digital verification engineer.
Medium Access Control layer of 802.15.4
An abstraction library for interfacing EDA tools
UVM resource from github, run simulation use YASAsim flow
FuseSoC is a package manager and a set of build tools for FPGA/ASIC development
gdb python scripts for SystemC design introspection and tracing
Git extensions to provide high-level repository operations for Vincent Driessen's branching model.
支持SHA-512/224 SHA-512/256算法的Gmssl分支
Embedded Programming with the GNU Toolchain
Main repo for Go2UVM source code, examples and apps
Honcho: a python clone of Foreman. For managing Procfile-based applications.
Job runner with logging
TCP/IP controlled VPI JTAG Interface.
first_tensorflow from Andrew Ng deep learning course2 week3 homework
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
:dragon_face:Jude's vimrc for DV work(fine tuning for SV/UVM)
Network on Chip Simulator
:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
pypyr task-runner cli & api for automation pipelines. Automate anything by combining commands, different scripts in different languages & applications into one pipeline process.
Accellera (http://www.accellera.org) IP-XACT (SPIRIT) Python Class Bindings
Uset systemRDL to generate UVM regmodel or Verilog C use header files
:beetle:Generate C/Verilog header file from compiled SystemRDL input
Code for the second edition of Advanced UVM.
make your verilog DUT test more smart
A snake game simulation
SystemVerilog BFMs with bindings for UVM, etc
YosysHQ SVA AXI Properties
This project is used to develop a script to support the preprocess code that defined in System RDL spec 1.0.
System Verilog
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.