zhangzek Goto Github PK
Name: Zekun.Zhang
Type: User
Zekun.Zhang's Projects
3x3_matrix_systolic_array_multiplier
3×3脉动阵列乘法器
booth_algorithm_multiplier
Booth算法乘法器专题
clock-domain-crossing-design
Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计
daily_fudan_actions
daily_fudan的运行器，自动定时执行https://github.com/Limour-dev/daily_fudan_core 的代码
daily_fudan_core
daily_fudan的代码，无需fork；请fork https://github.com/Limour-dev/daily_fudan_actions 来自动执行该repo下的最新代码
doc
Documentation for NVDLA.
e200_opensource
The Ultra-Low Power RISC Core
eyeriss-chisel3
eyeriss-chisel3
hardware_implementation_of_odd-even-sort_algorithm
奇偶排序算法的硬件实现
hardware_implementation_of_rgb_to_gray
【Verilog&vivado】彩色图像转灰度的硬件实现
kamikaze
Light-weight RISC-V RV32IMC microcontroller core.
mriscv
A 32-bit Microcontroller featuring a RISC-V core
mriscvcore
A 32-bit RISC-V processor for mriscv project
rgb-image-similarity-comparison-algorithm-
RGB image similarity comparison algorithm
risc-v-on-pynq
RISC-V Integration for PYNQ
sdram_controller
SDRAM_controller
simple-2d-convenience
简易二维卷积
soc-design-ddr3-controller
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
softmax_accelerator
DNNs中加速器SoftMax单元的设计
stream-ebpc
Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Lukas Cavigelli, Georg Rutishauser, Luca Benini.
sync_and_asyn_fifo
同步与异步FIFO
tinyriscv
A very simple and easy to understand RISC-V core.
uart_in_verilog
uart串口通信Verilog实现
verilog-axi
Verilog AXI components for FPGA implementation
verilog-pcie
Verilog PCI express components
zhangzek.github.io
MyBlog
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