zhihuasun Goto Github PK

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zhihuasun's Projects

64pointfftprocessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

a-single-path-delay-32-point-fft-processor

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

cfu

RISC-V FPGA SIG Custom Function Unit Specification

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

corundum

Open source FPGA-based NIC and platform for in-network compute

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

design-and-implementation-of-the-low-pass-digital-filter

- Implemented 6th order low-pass digital filter for a speech signal sampled at 44KHz in Matlab FDA tool. - Created quantized RTL(second order filter instanciated thrice) in Verilog with the coefficients represented with 12 bits and maintained SNR of 36.89. - Analyzed the correlation of the Verilog implementation against the Matlab filter implementation by a self-checking script that compared the output of the Verilog implementation versus the Matlab output of the quantized filter and found the error to be 0%.

design-and-verification-of-ldpc-decoder

- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.