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3d-ld-ecg

academicpages.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

convolutional-neural-network

Implementation of CNN using Verilog

ecg-signal-pre-processing-using-nlms-lms-adaptive-filters

In this project, the LMS and NLMS adaptive filters are implemented to remove the baseline wander, EMG and motion artifacts from a given signal and compare the results to deduce important distinctions regarding the respective performances.

fpga-implementation-of-precise-convolutional-neural-network-for-extreme-learning-machine

Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require more computation time. Extreme Learning Machines (ELM’s) are time-efficient, and they are less complicated than the conventional gradient-based algorithm. In previous years, an SRAM based convolutional neural network using a receptive – field Approach was proposed. This neural network was used as an encoder for the ELM algorithm and was implemented on FPGA. But, this neural network used an inaccurate 3-stage pipelined parallel adder. Hence, this neural network generates imprecise stimuli to the hidden layer neurons. This paper presents an implementation of precise convolutional neural network for encoding in the ELM algorithm based on the receptive - field approach at the hardware level. In the third stage of the pipelined parallel adder, instead of approximating the output by using one 2-input 15-bit adder, one 4-input 14-bit adder is used. Also, an additional weighted pixel array block is used. This weighted pixel array improves the accuracy of generating 128 weighted pixels. This neural network was simulated using ModelSim-Altera 10.1d and synthesized using Quartus II 13.0 sp1. This neural network is implemented on Cyclone V FPGA and used for pattern recognition applications. Although this design consumes slightly more hardware resources, this design is more accurate compared to previously existing encoders.

fpga_image_processing

IP operations in verilog (simulation and implementation on ice40)

graph-rag

A graph rag for PDFs based on langchain and Neo4j. Can fetch PDFs from Zotero Library through zotero api.

helloword-keyboard

oslw_code

Code for OSLW

upduino-v3.0

UPduino 3.0: new 4 layer layout, various other improvements

wetac