Comments (1)
Problem is fixed in AMF-Placer 2
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Related Issues (11)
- SLR/Clock/Congestion-Aware Initial Placement
- Could not find "Q_WS_WIN", "Q_WS_QWS" and "Q_WS_MAC" during the cmake HOT 1
- can't reach patoh-Linux-x86_64.tar.gz HOT 2
- Can i have the original design and device file of the VCU108? HOT 1
- reorganize the architecture of the placer and make processors act like LLVM passes(TODO) HOT 1
- After introducing timing optimization, some half-column clock regions get legalization violation (will be solved soon) HOT 1
- WARNING: We are integrating the timing-driven functions and it might lead to unstable problems of benchmark "OptimSoC" HOT 2
- Please don't hesitate to contact us if you encounter problems with our AMF-Placer
- Extension to other Xilinx FPGA device HOT 5
- Timing-driven FPGA Placement enabled HOT 1
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