Name: Hans_Pham
Type: User
Company: HCM University of Technology
Bio: love tech and futurism
currently interested in TPU,CPU,GPU,NPU.
My youtube channel:
https://www.youtube.com/channel/UCZNl3FZHM5c8cAVC68Z0poA
Location: Ho Chi Minh city, Viet Nam
Blog: https://www.linkedin.com/in/kha%CC%89i-pha%CC%A3m-t%C3%A2%CC%81n-100540191/
Hans_Pham 's Projects
lowRISC Style Guides
SystemVerilog Tutorial
SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
Practice exercises for SystemVerilog, UVM ..
This is a repo where I share the System Verilog exercises that I worked on. Contributions and suggestions are welcome
The source code of blog
PDFs of my publications
Python Tool for UVM Testbench Generation
Optimizing Deep Convolutional Neural Network with Ternarized Weights and High Accuracy
New open source Hyperram IP
A python project to automatically generate the UVM testbench document.
Krishna's my_verilog Contains HDL(Hardware Description Language) verilog codes for adders and multipliers.Work done as an assignment in Banashree Renewable Energy Systems Pvt. Ltd
Various caches written in Verilog-HDL
Programas en Verilog y SystemVerilog empleando ModelSim Student Edition
sample verilog design
Verilog/SystemVerilog Syntax and Omni-completion