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SISO vector decoder for IRA-LDPC codes in VHDL

Prerequisites:

• GHDL to simulate VHDL.
• GNU Make to use the Makefile for building.
• GTKWave to view the waveforms generated by the simulation.
• C++ compiler to build the test vector generators.

Run make vector to build and simulate vector versions of the check node processor and decoder.

Compare resulting cnp_vector_tb_out.txt with cnp_vector_tb_exp.txt for the check node processor.

Compare resulting dec_vector_tb_out.txt with dec_vector_tb_exp.txt for the decoder.

Run make scalar to build and simulate scalar versions of the check node processor and decoder.

Compare resulting cnp_scalar_tb_out.txt with cnp_scalar_tb_exp.txt for the check node processor.

Compare resulting dec_scalar_tb_out.txt with dec_scalar_tb_exp.txt for the decoder.

Run make vcd to generate scalar version waveforms and watch them via gtkwave cnp_scalar_tb.vcd.

Checkout tables for suitable code tables.

Store new table in table_scalar.txt while making sure that the constants in ldpc_scalar.vhd and ldpc_scalar.hh match.

Run make scalar to see if the new table is free from data hazards by comparing dec_scalar_tb_out.txt with dec_scalar_tb_exp.txt.

Checkout tables for suitable code tables.

Store new table in table_vector.txt while making sure that the constants in ldpc_scalar.vhd, ldpc_vector.vhd, ldpc_scalar.hh and ldpc_vector.hh match.

Run make vector to see if the new table is free from data hazards by comparing dec_vector_tb_out.txt with dec_vector_tb_exp.txt.

• Interface for switching or replacing code table
• Shortening the pipeline if timing analysis allows it
• More corner case testing and documentation
• Can the interface be improved?

• Self-Corrected Min-Sum
• Scalar and Vector versions
• Min-Sum or Offset-Min-Sum with fixed beta = 1
• Pipelined processing
• Write disable flags to resolve write conflicts with DDSMs
• Reference decoder in C++
• Tool for checking code table entries for data hazards
• Tool for enforcing below rules for code table entries
• Reduced table size for scalar decoder
• Tool for generating code table entries

scalar LDPC decoder configuration

scalar LDPC decoder configuration

vector LDPC decoder configuration

vector LDPC decoder configuration

Transformed DVB T2 B7 code table for scalar decoder:

• Rows are sorted by location offsets to maximally space out same offsets on consecutive columns.
• Columns are sorted by count to minimize pipeline stalls.

Transformed and manipulated DVB T2 B7 code table for vector length of 15:

• Rows are sorted by location offsets to keep same offsets consecutive.
• Above sorting helps maximally spacing out same offsets on consecutive columns.
• Swapped columns to avoid same offsets on consecutive columns.
• Columns are sorted by count to minimize pipeline stalls.

check table_scalar.txt for data hazards

The following rules must apply to the table for the decoder to work correctly:

• Order of location offsets must avoid data hazards caused by the pipeline.
• Optional: Keep same count rows consecutive to avoid pipeline stalls.

check table_vector.txt for data hazards

The following rules must apply to the table for the decoder to work correctly:

• Rows containing DDSMs must keep locations with same offset consecutive.
• Order of location offsets must avoid data hazards caused by the pipeline.
• Optional: Keep same count rows consecutive to avoid pipeline stalls.

code table generated from table_vector.txt by generate_table_vector_vhd.cc

testbench for the scalar check node processor

testbench for the vector check node processor

testbench for the scalar decoder

testbench for the vector decoder

SISO scalar decoder for IRA-LDPC codes

SISO vector decoder for IRA-LDPC codes

scalar check node processor

vector check node processor

buffer for the scalar check node processor

generate cnp_scalar_tb_inp.txt from random noise

generate cnp_scalar_tb_exp.txt processed from cnp_scalar_tb_inp.txt

buffer for the vector check node processor

generate cnp_vector_tb_inp.txt from random noise

generate cnp_vector_tb_exp.txt processed from cnp_vector_tb_inp.txt

Generate dec_vector_tb_inp.txt from random noise

Generate dec_vector_tb_exp.txt decoded from dec_vector_tb_inp.txt

Generate table_vector.vhd from table_vector.txt

Generate table_model.txt from table_input.txt

This formulates a linear programming model of the code table to solve potential data hazards.

Generate table_vector.txt from table_input.txt and table_solution.txt

The solution table_solution.txt of the problem formulated in table_model.txt is used to permutate the lines in table_input.txt to create a data hazard free table_vector.txt.

scalar saturating addition

vector saturating addition

rotate left vector elements

rotate right vector elements

scalar bit node links

vector bit node links

counts for the vector decoder

locations for the vector decoder

scalar variable nodes

vector variable nodes

write disable flags for the vector decoder

Reduce N times while excluding ith input element

It computes the following, but having only O(N) complexity and using O(1) extra storage:

	output[0] = input[1];
	output[1] = input[0];
	for (int i = 2; i < N; ++i)
		output[i] = op(input[0], input[1]);
	for (int i = 0; i < N; ++i)
		for (int j = 2; j < N; ++j)
			if (i != j)
				output[i] = op(output[i], input[j]);

scalar check node processor reference code

The C++ code below is also included in cnp_scalar.hh:

void cnp(int *output, const int *input, int cnt, int beta)
{
	int imags[cnt];
	for (int i = 0; i < cnt; ++i)
		imags[i] = min(max(abs(input[i]) - beta, 0), 31);

	int omags[cnt];
	CODE::exclusive_reduce(imags, omags, cnt, min);

	int isgns[cnt];
	for (int i = 0; i < cnt; ++i)
		isgns[i] = sgn(input[i]);

	int osgns[cnt];
	CODE::exclusive_reduce(isgns, osgns, cnt, mul);

	for (int i = 0; i < cnt; ++i)
		output[i] = osgns[i] * omags[i];
}

vector check node processor reference code

scalar IRA-LDPC decoder reference code

vector IRA-LDPC decoder reference code