Language: Verilog.
1- Invertor. 2- Multiplixer 2:1. 3- AND-ing 8-bits. 4- Muliplixer 4:1. 5- Full Adder.
1- OR_gate6.v 2- Testbench_org_gate6.v
1- MULTIPLIXER.v 2- testbench_MULTIPLIXER.v
1- flopr.v 2- testbench_flopr.v 3- FuLL ADDER NON-BLOCKING