andrecurvello / implementation-of-simplified-tcp-using-the-nios-ii-in-intel-de2i-150-fpga-board. Goto Github PK

This project forked from tzechienchu/implementation-of-simplified-tcp-using-the-nios-ii-in-intel-de2i-150-fpga-board.

Created Qsys system that includes Nios II, Triple-Speed Ethernet IP Core, SGDMA controller and other hardware components for transmit and receive operation. Two Phase-Locked Loop modules are added to the design to generate clocks with different frequencies to make the Triple-Speed Ethernet system (which implements the MAC function) work properly at 10/100/1000 Mbps. After building the hardware system and downloading the circuit onto the FPGA, run an application program written in C language. Based on the inputs from the board it establishes and closes the TCP connection, transmit and receive data frames from the Ethernet port of the board. Ethernet frames are transmitted based on Stop and Wait Protocol and Altera Timer core is added to re-transmit frames after Timeout.