antmicro / alkali-csd-hw Goto Github PK

The link to the repository, alkali-csd-hw. I have been trying to build the project, while I issued the "make all" command, during "make vivado" command the building has been failing, has it cannot the design due to the following errors, ( I got when I ran "source vivado_block_design.tcl" vivado (version 2019.2)

INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:axi_protocol_converter:2.1 xilinx.com:ip:axi_uartlite:2.0 xilinx.com:ip:ila:6.2 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:system_management_wiz:1.3 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:zynq_ultra_ps_e:3.3 xilinx.com:hls:compute:1.0 xilinx.com:hls:fetch:1.0 xilinx.com:ip:fifo_generator:13.2 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:hls:load:1.0 xilinx.com:ip:smartconnect:1.0 xilinx.com:hls:store:1.0 .
WARNING: [Coretcl 2-175] No Catalog IPs found
WARNING: [Coretcl 2-175] No Catalog IPs found
WARNING: [Coretcl 2-175] No Catalog IPs found
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD_TCL-115] The following IPs are not found in the IP Catalog:
xilinx.com:hls:compute:1.0 xilinx.com:hls:fetch:1.0 xilinx.com:hls:load:1.0 xilinx.com:hls:store:1.0

Resolution: Please add the repository containing the IP(s) to the project.
WARNING: [BD_TCL-1003] Will not continue with creation of design due to the error(s) above.

To resolve the issue, I tried to add the missing IPs from the IP catalogue in the vivado. But, unfortunately I was not able to find any of the missing IPs in the catalogue.

System - Ubuntu 18.04.6 LTS
Kernel version - 4.15.0-204-generic

Please help me find a way to resolve the issues and successfully build the project. Thanks in advance

Hello,

Error occurred while installing the required python packages
Command - pip3 install -r requirements.txt

Hey!

I'm running into an issue where the host machine is unable to read the nvme registers (CAP, VER, CSTS) etc... I can see the scala implementation for embedding the values into the RO registers . But unsure why these are not read. For instance, I can read them from Zephyr but the host side does not. See below the result of the nvme show-regs command. Where all registers are 0, when they should not be.

Is it possible that the host csr access is hooked up incorrectly (Not super familiar with how scala/chisel works... So no idea)

for instance here?

Thanks!