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tiliqua's Introduction

Tiliqua

WARN: ๐Ÿšง under construction! ๐Ÿšง - this module is in active development

Tiliqua is a powerful, open hardware FPGA-based audio multitool for Eurorack.

For updates, subscribe to the Crowd Supply page and my own mailing list

Technical

Audio Interface

  • 8 (4 in + 4 out) DC-coupled audio channels, 192 KHz / 24-bit sampling supported
  • Touch and proximity sensing on all 8 audio jacks (if unused)
  • PWM-controlled, user-programmable red/green LEDs on each audio channel
  • Jack insertion detection on all 8 jacks

Motherboard

  • Switched rotary encoder with bar graph display.
  • Dual USB ports:
    • dbg: Included RP2040-based JTAG debugger supported by openFPGAloader
    • usb2: USB PHY connected directly to FPGA for high-speed USB Audio support
  • Display output for video synthesis (maximum resolution 720/60P)
  • 2x expansion ports for up to 24 simultaneous audio channels (PMOD-compatible)
  • MIDI-In jack (TRS-A standard)

Embedded FPGA SoM (soldiercrab)

  • Lattice ECP5 (25 K) FPGA, supported by open-source FPGA toolchains
  • 128 Mbit (16 MByte) HyperRAM / oSPI RAM (for long audio buffers or video framebuffers)
  • 128 Mbit (16 MByte) SPI flash for user bitstreams
  • High-speed USB HS PHY (ULPI)

Where do I get a Tiliqua?

Tiliqua will launch on Crowd Supply. Subscribing there is the best place to get production updates.

Getting Started

Building example projects

On an Ubuntu system, the following are the main dependencies:

  • The build system: install pdm
  • For synthesis: install oss-cad-suite
  • For examples that include a softcore: rust.
    • To build stripped images for RISC-V, you also need:
      • rustup target add riscv32imac-unknown-none-elf
      • rustup component add rustfmt clippy llvm-tools
      • cargo install cargo-binutils svd2rust form

To set up the environment:

cd gateware
# fetch eurorack-pmod verilog sources
git submodule update --init --recursive
# install all python requirements to a local .venv
pdm install

To build some examples:

# for the LUNA-based 4in + 4out USB soundcard example
pdm build_usb_audio
# for a 4-channel waveshaping oscillator
pdm build_dsp_core nco
# for a diffusion delay effect
pdm build_dsp_core diffuser
# for a polyphonic MIDI synth
pdm build_dsp_core midipoly
# for the vectorscope / DVI example
pdm build_vectorscope
# for an SoC example (selftest with RISCV softcore)
pdm build_selftest
# (WIP) vectorscope + SoC + menu system
pdm build_xbeam

Generally, bitstreams are also built in CI - check .github/workflows if you need more gruesome details on how systems are built.

Flashing example projects

The built-in RP2040 JTAG debugger is based on the dirtyJtag project. You can flash the bitstreams above to the SRAM of the FPGA like so (add an -f to instead flash it to SPI flash permanently):

sudo openFPGALoader -c dirtyJtag build/top.bit

If you are running an SoC, it will give you serial output that you can monitor like so:

sudo picocom -b 115200 /dev/ttyACM0

Simulating DSP cores

The easiest way to debug the internals of a DSP project is to simulate it. This project provides some shortcuts to enable simulating designs end-to-end with Verilator, which is much faster at crunching numerically heavy designs than Amaranth's built-in simulator.

For example, to simulate the waveshaping oscillator example:

pdm sim_dsp_core nco

A lot happens under the hood! In short this command:

  • Elaborates your Amaranth HDL and convert it to Verilog
  • Verilates your verilog into a C++ implementation, compiling it against sim_dsp_core.cpp provided in gateware/example_dsp that excites the audio inputs (you can modify this).
  • Runs the verilated binary itself and spits out a trace you can view with gtkwave to see exactly what every net in the whole design is doing.

Builds on the following (awesome) open-hardware projects

License

The hardware and gateware in this project is largely covered under the CERN Open-Hardware License V2 CERN-OHL-S, mirrored in the LICENSE text in this repository. Some gateware and software is covered under the BSD 3-clause license - check the header of the individual source files for specifics.

Copyright (C) 2024 Sebastian Holzapfel

The above LICENSE and copyright notice do NOT apply to imported artifacts in this repository (i.e datasheets, third-party footprints), or dependencies released under a different (but compatible) open-source license.

tiliqua's People

Contributors

schnommus avatar

Stargazers

Ryohei Niwase avatar Brian Dorsey avatar Zachary Michels avatar Matthew avatar Peter Vrba avatar Kayla Firestack avatar  avatar Mark Santolucito avatar Martin Ling avatar  avatar Pavlo Shelemba avatar  avatar Johannes Lohbihler avatar VanTa avatar Tom Burdick avatar Tyler Neely avatar Benjamin van der Burgh avatar Shakeeb Alireza avatar mat kelcey avatar

Watchers

 avatar Benjamin van der Burgh avatar

Forkers

pawpawdeng

tiliqua's Issues

Known Issues: Tiliqua R2.0

Some known issues and notes on bringing up the R2.0 beta units:

  • WARN: always use the tiliqua mobo bus power ingress. The other 12V bus power (going straight into eurorack-pmod) has no polyfuse.

eurorack-pmod PCBA

  • Capsense IC stays in reset if jack 2 (starting at 0) is inserted before cold powerup. Workaround is already in gateware, see apfelaudio/eurorack-pmod#59

tiliqua-mobo PCBA

  • Polyfuse too low for ~500mA max. current draw when Tiliqua is used to source current in USB host mode.
    • No USB host example projects yet, need this for validation
    • I tried drawing this kind of current, nothing blows up. The tiliqua will just turn off and the built-in polyfuse resets 30sec later.
    • Using the eurorack-pmod power ingress instead is an easy workaround for host testing
  • Encoder locating pin sticks out too far.
  • V-Score slightly too close to panel, causing tilt on mobo PCBA. A shim washer on the encoder should also help with this.

soldiercrab PCBA

  • LEDs are too bright, current limiting resistors should be larger.
  • Gets a bit warm (but not too hot to touch). Ground mounting hole on both sides for better heatsinking & shielding. Switching to smaller ECP5/PSRAM should also help with this alongside 3V3 -> 1V8 on the PSRAM/USB PHY rails.
  • Increase copper clearance at edges to reduce dimensions on all sides by ~0.2mm

panel PCBA

  • Plate slots for DVI/USB for better shielding
  • Fix DVI panel cutout, it's close but not perfect
  • Fix rounding on the LED encoder ring cutout.

proto1 bringup // 04.24

BUGS found

  • rp2040 doesn't enter bootloader:
    • fix: rp2040 assumes 2V5 rail that doesn't exist. Fix: bridge C7 + C10
  • rp2040 doesn't exit bootloader:
    • fix: too much pull on SPI flash CS. Fix: remove C17
  • fpga won't self-configure
    • fix: applecrab initn pd should be removed
  • 3V3 line is noisy and ~3.15V instead of 3.3V
    • Switch to 5V buck with post-regulator (linear)?
  • Power from USB doesn't work with jumper set
    • Remove this feature OR add single -5V supply such that analog rails work off of USB only (test swing?)

BRINGUP done:

  • test hyperram @ full-speed (240MB/sec) reliable
  • test fpga flash / config / readback
  • test RP2040 debugging
  • test USB2 PHY
  • test eurorack-pmod interface and noise

ADMIN:

  • take some nice pictures, publish repo as UNDER CONSTRUCTION
  • get open hardware certification ID
  • get open USB PID/VID
  • next revision: get CE cert and gather docs
  • 2xusb // 90deg + uhdmi + encoder + sd (opt)

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