Related Issues (20)
- Make CLINT/PLIC CXXRTL models and run them under qemu or spike HOT 1
- More CSR Tests
- Fix image docker versions HOT 1
- AXI Register Slice
- Fetch: New branch taken implementation with pending active Cache request canceling HOT 1
- Fetch: stress test using verilator
- New Pipelined Cache architecture with 3 cycle deep pipeline HOT 1
- Skywater130 tapeout
- QSPI Flash and QSPI PSRAM controller HOT 1
- Interrupt after branch taken contains incorrect PC
- Verilator Lints: Remove global lint off-s
- Fix Cache implementation HOT 1
- Implement CSR remaining commands
- Add more tests testing limits of TLB (including victim_way checking)
- Cache: REQ READY undriven HOT 1
- Exclusive monitor implementation is wrong. More optimal solution is possible. HOT 4
- Remove response stage from Cache. Let it be responsibility of the pipeline itself. This solution is more optimal. HOT 1
- AXI4 Router needs more tests HOT 1
- RISC-V Timer can be optimized
- axi_bram has fixed width because of 1rwm address logic
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