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The MEIP field in mip is a read-only bit that indicates a machine-mode external interrupt is
pending. MEIP is set and cleared by a platform-specific interrupt controller. The MEIE field in
mie enables machine external interrupts when set.
The SEIP field in mip contains a single read-write bit. SEIP may be written by M-mode software to indicate to S-mode that an external interrupt is pending. Additionally, the platformlevel interrupt controller may generate supervisor-level external interrupts. The logical-OR of the
software-writable bit and the signal from the external interrupt controller is used to generate external interrupts to the supervisor. When the SEIP bit is read with a CSRRW, CSRRS, or CSRRC
instruction, the value returned in the rd destination register contains the logical-OR of the softwarewritable bit and the interrupt signal from the interrupt controller. However, the value used in the
read-modify-write sequence of a CSRRS or CSRRC instruction is only the software-writable SEIP
bit, ignoring the interrupt value from the external interrupt controller.

Make sure all tests have $fatal and $display w/ !ERROR!

1. Reduce minimal value of LANE_W
2. AXI4 Bus
3. Redesign Cache to be write-through
4. AXI4 Wrap Burst
5. Atomic operations

AXI4 Cache starts reading cache line from the requested address offsett and returns value before request is done

Implement HTIF interface to use by verif-isa-tests to validate core. Do it with Icarus Verilog to ensure maximum compatibility.
Icarus Verilog does not return an error code from Verilog, so do it by writing a special value in the log. Also, dump data section to compare with reference.

See: riscv-software-src/riscv-isa-sim#364 for HTIF protocol

When D-Cache is flushed data in memory is written. But when I-Cache is flushed data is not invalidated in cache, causing data in I-Cache to be stale

Stop relying on default net type and add "wire" definition for all.

JALR/JAL is not ignoring LSB bit.

Add debug capabilities

Instead of keeping 2 stages have multiple stage:
Prefetch, fetch, decode, execute, mem, writeback.

Replace I/D-bus with AXI4 so that it can be simply pipelined.

Move assertions/debug statements from combinational to sequential section

Implement Chip2Chip protocol.
Max burst of 16 x 32.
Send 8-bit opcode, then the payload.
8 bit for data; + one csn, one oe = 10 pins
Skywater130 is 33MHz maximum => 33Mbps per pin x 8 bits = ~33MBps of raw speed per direction.
Clock is provided common between devices.
Two symmetrical interfaces, one host and one client on each chip.

As the interface is symmetrical, the same logic interface is implemented the other way around

Redesign ALU so it will not depend on ISA, instead it will only use value of select signals.

1. Make multiplication do it in two cycles
2. Move sign inversion out of execute and merge together
3. Optimize division to do it in less than 32 cycles

Cache/Backstorage
CacheCoherency
Atomics
Cache separate bus
Cache bus to AXI4 with cache coherency

Add armleocpu_undef.vh that undefines all defines. Same for armleocpu_csr.v which contains additional defines