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Top-level repository for the ACT EDA flow

Home Page: https://avlsi.csl.yale.edu/act/

License: GNU General Public License v2.0

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act cad eda vlsi asynchronous asynchronous-circuits asynchronous-vlsi self-timed

actflow's Introduction

The ACT flow for implementing asynchronous logic

This repository contains the key modules required to use the ACT implementation flow for asynchronous logic. The parallel algorithms used in the implemention flow use a combination of OpenMP and the Galois library.

Dependencies

The Galois library depends on the following:

A modern C++ compiler compliant with the C++-17 standard (gcc >= 7, Intel >= 19.0.1, clang >= 7.0)
CMake (>= 3.16)
Boost library (>= 1.71.0, we recommend building/installing the full library)
libfmt (>= 4.0)

More details about optional features/etc. are available. Note that while the Galois library does depend on the LLVM compiler infrastructure, we are only using a small part of the library so we have eliminated this dependency for actflow.

The ACT library depends on the following:

The system must have libedit installed. For the yum package manager, the package is called libedit-devel; for apt-get, it is libeditline-dev. Some systems have both packages. In that case please use libedit, not libeditline.
The system should have zlib installed
The system should have the macro pre-processing package m4 installed

The expression optimization library uses the abc logic synthesis and verification library from Berkeley. It can also use yosys, if the binary is installed on your system. The README provided by yosys has detailed installation instructions.

Your system may have an older version of the Boost libraries installed. If you cannot update those and need to install a more modern version of Boost in a different directory, then you can point the build process to your new Boost library location by setting the BOOST_ROOT environment variable to the new install directory.

Steps

Pick an installation directory for all the tools, and set the environment variable ACT_HOME to this directory. Create this directory.
Make sure you have all the submodules needed as well (git submodule update --init --recursive), if you didn't clone the repo with all the submodules.
Run ./build

This should build and install all the libraries and tools needed.

If you'd like to delete all the files generated during the build process, run ./clean

References

If you use this flow for a publication, we would appreciate a citation to the following overview paper that summarizes the flow:

Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali, "An Open-Source EDA Flow for Asynchronous Logic," in IEEE Design & Test, vol. 38, no. 2, pp. 27-37, April 2021, doi: 10.1109/MDAT.2021.3051334.

actflow's People

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bics-rug isaeldiaz

actflow's Issues

Net propagation detected two nets are shorted

Observed behavior
Act believes that there are shorted signals when there arent when observed in layout

Expected behavior
Act should accept the rect file and be prepared for placement.

Potential complications
I'm not sure if this is the correct format for the .rect files. The documentation regarding the layer names isn't very clear. It may also be that ACT expects the pull-up stack to be on top while floret puts the pull-down stack on top. This could be fixed fairly easily, but it also shouldn't matter from ACT's perspective.

Files

prs2net.conf.txt
layout.conf.txt

/opt/cad/conf/sky130/cells/rect/_0_0cell_0_0g0n_0x0.rect

bbox -73 -61 207 323
inrect GND m1 0 213 34 297
inrect Vdd m1 0 0 34 84
inrect in[0] m1 0 128 66 162
outrect out m2 88 190 146 236
rect # ndiff -12 213 146 297
rect # nwell -73 -61 207 145
rect # pdiff -12 0 146 84
rect GND ndc 0 238 34 272
rect GND pc 0 238 34 272
rect Vdd pc 0 25 34 59
rect Vdd pdc 0 25 34 59
rect in[0] ndc 16 128 50 162
rect in[0] pc 16 128 50 162
rect in[0] polysilicon 0 118 66 172
rect in[0] polysilicon 52 -26 82 323
rect # svtnfet 52 213 82 297
rect # svtpfet 52 0 82 84
rect out m1 100 0 134 297
rect out m1 88 196 146 230
rect out mcon 100 196 134 230
rect out ndc 100 196 134 230
rect out ndc 100 238 134 272
rect out pc 100 238 134 272
rect out pc 100 25 134 59
rect out pdc 100 25 134 59

test.act

defproc testbench(bool a, b)
{
	preal n1 = 6.0;

	prs
	{
		a<n1> -> b-
		~a<n1> -> b+
	}
}

bool a, b;
testbench dut(a, b);

interact.conf

act:read "test.act"
act:merge "cells.act"
act:expand
act:top testbench
ckt:cell-map
ckt:map
ckt:cell-save "cells.act"
ckt:save-sp "cells.spi"
load-scm "phydb.scm"
phydb:create 1.8 1  "output.lef"

$ touch cells.act
$ interact -ref=1 -Tsky130
interact> source interact.conf
WARNING: Tile::addRect() failed; inconsistent tile types being merged
WARNING: Tile::addRect() failed; inconsistent tile types being merged
WARNING: [g0n_0x0<>] Missing lower base layer at (100,196)?
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: GND; net2: out
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: Vdd; net2: out
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: out; net2: GND
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: out; net2: Vdd
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: GND; net2: out
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: Vdd; net2: out
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: out; net2: GND
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: out; net2: Vdd
WARNING: [g0n_0x0<>] Missing lower base layer at (100,196)?
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: GND; net2: out
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: Vdd; net2: out
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: out; net2: GND
WARNING: [g0n_0x0<>] Net propagation detected two nets are shorted.
	net1: out; net2: Vdd
WARNING: [g0n_0x0<>] Missing lower base layer at (100,196)?
WARNING: g0n_0x0<>: center diffusion spacing asjusted (orig: 54; .rect: -297); using .rect file value

rect script

rect -gds /opt/cad/conf/sky130/cells/rect/_0_0cell_0_0g0n_0x0.rect

preal rule sizing breaks ACT's ability to map cells

Steps to Reproduce

$ touch cells.act
$ interact -ref=1 -Tsky130
interact> source interact.conf
WARNING: new cells generated; please update your cell library.
(Use ckt:cell-save to see the new cells.) New cell names are:
   g0n_0x0
interact> quit
$ interact -ref=1 -Tsky130
interact> source interact.conf
WARNING: new cells generated; please update your cell library.
(Use ckt:cell-save to see the new cells.) New cell names are:
   g0n_0x1
interact> quit

test.act

defproc testbench(bool a, b)
{
	preal n1 = 6.0;

	prs
	{
		a<n1> -> b-
		~a<n1> -> b+
	}
}

bool a, b;
testbench dut(a, b);

interact.conf

act:read "test.act"
act:merge "cells.act"
act:expand
act:top testbench
ckt:cell-map
ckt:map
ckt:cell-save "cells.act"
ckt:save-sp "cells.spi"
phydb:init

Expected behavior
interact is able to recognize same cells

Suspected Reason
The cell looks to be saved with integer sizing parameters whereas it was originally generated with real sizing parameters.

export defcell g0n_0x0 (bool? in[1]; bool! out)
{
   prs {
   in[0]<6> -> out-
   ~in[0]<6> -> out+
   }
}

Versions
Most recent commit actflow (6ba25cf)
$ lsb_release -a
Distributor ID: Ubuntu
Description: Ubuntu 22.04.4 LTS
Release: 22.04
Codename: jammy

asyncvlsi / actflow Goto Github PK

actflow's Introduction

The ACT flow for implementing asynchronous logic

Dependencies

Steps

References

actflow's People

Contributors

Stargazers

Watchers

Forkers

actflow's Issues

Net propagation detected two nets are shorted

preal rule sizing breaks ACT's ability to map cells

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