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AMC: Asynchronous Memory Compiler

Home Page: http://avlsi.csl.yale.edu/act/doku.php?id=amc:start

License: GNU General Public License v2.0

Python 97.72% Shell 0.03% C 0.15% TeX 0.10% AMPL 0.66% SourcePawn 0.25% HCL 1.09%

eda asynchronous-sram asynchronous-vlsi design-automation vlsi

amc's Introduction

AMC : An Asynchronous Memory (SRAM) Compiler.

AMC is an open-source asynchronous pipelined memory compiler. AMC generates SRAM modules with a bundled-data datapath and quasi-delay-insensitive control. AMC is a Python-base, flexible, user-modifiable and technology-independent memory compiler that generates fabricable SRAM blocks in a broad range of sizes, configurations and process nodes.

The description of the circuits AMC generates and the compiler can be found in the following paper:

Samira Ataei and Rajit Manohar. AMC: An Asynchronous Memory Compiler. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2019.

AMC generates GDSII layout data, standard SPICE netlists, Verilog models, DRC/LVS verification reports, timing and power models (.lib), and placement and routing models (.lef).

More detailed documentation is available here: http://avlsi.csl.yale.edu/act/doku.php?id=amc:start

Copyright Notice

AMC is licensed under GNU General Public License v2.0. AMC project originated from the OpenRAM code (https://github.com/VLSIDA/OpenRAM) version 7b5791b from May 9, 2018, developed by Matthew Guthaus from UC Santa Cruz VLSIDA group as the lead architect and also contributed to by Samira Ataei. AMC developers have made a large number of changes that have to do with changing the memory interface circuits, supporting modern design rules and thin-cell SRAM layout, new partitioning and floorplanning, and different timing and characterization methodology. The organization of the code base mirrors the OpenRAM version 7b5791b. As OpenRAM is under BSD 3-Clause License, portions of code that are derived from OpenRAM remain under BSD license.

amc's People

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sataei superwind nimbis xinjie0831 cecijyx ocakgun tanvirarafin nmtrmail nguyentrungduong blaisefangman

amc's Issues

Output files not saved

If you run your example configuration, no output files are saved:

`$ python2 AMC.py example_config_scn3me_subm.py
|==============================================================================|
|==== ====|
|==== AMC: Asynchronous Memory Compiler ====|
|==== ====|
|==== version 1.0, 2018-2019 ====|
|==== ====|
|==== Computer Systems Lab ====|
|==== Yale University ====|
|==== ====|
|==============================================================================|

Output files are AMC_SRAM.(sp|gds|v|lib|lef)
** Start: 2019-07-23 10:01:42.196720 seconds

SP: Writing to PATH/tmp/AMC_SRAM.sp
** Spice writing: 0.0 seconds

GDS: Writing to PATH/tmp/AMC_SRAM.gds
** GDS: 0.3 seconds

LEF: Writing to PATH/AMC_SRAM.lef
** LEF: 1.2 seconds

Verilog: Writing to PATH/tmp/AMC_SRAM.v
** Verilog: 0.0 seconds
** End: 4.8 seconds
$ ls PATH/tmp
ls: tmp: No such file or directory`

Could you please add a LICENSE file?

What license is this released under? Could you add a LICENSE or COPYING file?

Thank you!

Fixing the LICENSE detection

There was a small modification to the LICENSE file,

diff --git a/LICENSE b/LICENSE
index 15f75cf..d159169 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,4 +1,4 @@
-GNU GENERAL PUBLIC LICENSE
+                    GNU GENERAL PUBLIC LICENSE
                        Version 2, June 1991
 
  Copyright (C) 1989, 1991 Free Software Foundation, Inc.,

Run wget https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt -O LICENSE to fix it.

Some errors in the generated verilog model file.

I am interested in the AMC, and tried it yesterday.
However, it seemed that there are some errors in the verilog model file which is generated from compiler/base/verilog.py.

The write data (data_in) is not used in the verilog model. Instead, the internal read data "DATA" is used as write data.
The address (addr) is not used in the verilog model. Instead, a unknow "ADDR" is used as address.
In addition, the acknowlege signal of address (ack), which should be a ouptut singal, is floating.
Another double quotation mark is requested after the string of MEM in $display($time, "Reseting MEM); .

LEF file errors

There are some errors in the LEF file that were fixed in OpenRAM, but have not been ported to AMC.

For example, library cells are entirely blocked rather that detailed blockages which will cause pin access errors in P&R.
In addition, the LEF file units are off by a few orders of magnitude which will result in a meter long memory sizes.

create_bist option

The example technology uses the create_bist option. However this option is not recognized by AMC.py

compiler/example_config_scn3me_subm.py
create_bist = True

Missing Copyright

This project was copied from OpenRAM, but the BSD license has not been followed. You are supposed to include the previous copyright. Please add this. Thanks!

Missing copyright in derived files

In the most recent commits, portions of the new unit tests are modified from OpenRAM yet the copyright has been removed. As a reminder, the copyright must be maintained "with or without modification".

Missing shebang line in AMC.py

First lines in Unix scripts generally start with the interpreter or a line to get the interpreter from the current path. Usually this looks like this:
#!/usr/bin/env python2
It is missing from AMC.py, so you cannot just type:
./AMC.py
but instead have to type:
python2 AMC.py

https://en.wikipedia.org/wiki/Shebang_(Unix)

Python 2.7 being deprecated

FYI, Python 2.7 is being deprecated on 1/1/2020. The current code has some 2.7 dependencies and doesn't work with Python 3.x.

No .lib file generated

The output files are listed as:
Output files are AMC_SRAM.(sp|gds|v|lib|lef)
However, there is no .lib file generated for use with synthesis.