ataylorcengfiet / fedevel Goto Github PK

[Synth 8-5535] port <sys_clock> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
	Port I of instance clkin1_ibufg(IBUF) in module <design_1_clk_wiz_0_0_clk_wiz>
Other Components:
	Port C of instance \U0/enb_led_reg (FD) in module design_1_led_fsm_0_0
	Port C of instance \U0/current_state_reg (FD) in module design_1_led_fsm_0_0
	Port C of instance \U0/led_enb_reg[0] (FD) in module design_1_led_fsm_0_0
	Port C of instance \U0/led_enb_reg[1] (FD) in module design_1_led_fsm_0_0
	Port C of instance \U0/led_enb_reg[2] (FD) in module design_1_led_fsm_0_0
	Port C of instance \ack_reg2_reg[0] (FD) in module ila_v6_2_12_ila
	Port C of instance trig_in_reg_reg(FD) in module ila_v6_2_12_ila
	Port C of instance \sync_reg1_reg[0] (FD) in module ila_v6_2_12_ila
	Port C of instance \shifted_data_in_reg[8][0] (FD) in module ila_v6_2_12_ila_core
	Port CLK of instance \shifted_data_in_reg[7][0]_srl8 (SRL16E) in module ila_v6_2_12_ila_core
	Port C of instance \shifted_data_in_reg[8][1] (FD) in module ila_v6_2_12_ila_core
	Port CLK of instance \shifted_data_in_reg[7][1]_srl8 (SRL16E) in module ila_v6_2_12_ila_core
	Port C of instance \shifted_data_in_reg[8][2] (FD) in module ila_v6_2_12_ila_core
	Port CLK of instance \shifted_data_in_reg[7][2]_srl8 (SRL16E) in module ila_v6_2_12_ila_core
	Port C of instance \shifted_data_in_reg[8][3] (FD) in module ila_v6_2_12_ila_core
	Port CLK of instance \shifted_data_in_reg[7][3]_srl8 (SRL16E) in module ila_v6_2_12_ila_core
	Port C of instance \shifted_data_in_reg[8][4] (FD) in module ila_v6_2_12_ila_core
        ... 

[Synth 8-2918] Failing due to illegal port connections

[Common 17-69] Command failed: Vivado Synthesis failed