aws / aws-fpga Goto Github PK

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

License: Other

Tcl 0.27% SystemVerilog 5.87% Makefile 0.01% Shell 0.05% Verilog 3.91% VHDL 84.52% Filebench WML 0.02% C 0.18% C++ 0.09% Python 0.09% Forth 0.01% Groovy 0.01% Pawn 0.01% V 4.98% NASL 0.01% Fortran 0.01% SourcePawn 0.01% Assembly 0.01%

Overview of AWS EC2 FPGA Development Kit

AWS EC2 FPGA Development Kit is a set of development and runtime tools to develop, simulate, debug, compile and run hardware accelerated applications on Amazon EC2 F1 instances. It is distributed between this github repository and FPGA Developer AMI - Centos/AL2 provided by AWS with no cost of development tools.

⚠️ NOTE: The developer kit is supported for Linux operating systems only.

Developer Support

Opening a GitHub Issue is the preferred method to get support with the AWS FPGA Development Kit. In addition, the FPGA Development re:Post Tag is available to find FPGA-related discussion topics from the AWS community of customers, AWS customer support, and the AWS FPGA development team.

Development Flow

After creating an FPGA design (also called CL - Custom logic), developers can create an Amazon FPGA Image (AFI) and easily deploy it to an F1 instance. AFIs are reusable, shareable and can be deployed in a scalable and secure way.

Development Environments

Development Environment	Description	Accelerator Language	Hardware Interface	Debug Options	Typical Developer
Software Defined Accelerator Development using Vitis/SDAccel	Development experience leverages an optimized compiler to allow easy new accelerator development or migration of existing C/C++/openCL, Verilog/VHDL to AWS FPGA instances	C/C++/OpenCL, Verilog/VHDL (RTL)	OpenCL APIs and XRT	SW/HW Emulation, Simulation, GDB, Virtual JTAG (Chipscope)	SW or HW Developer with zero FPGA experience
Hardware Accelerator Development using Vivado	Fully custom hardware development experience provides hardware developers with the tools required for developing AFIs for AWS FPGA instances	Verilog/VHDL	XDMA Driver, peek/poke	Simulation, Virtual JTAG	HW Developer with advanced FPGA experience
IP Integrator/High Level Design(HLx) using Vivado	Graphical interface development experience for integrating IP and high level synthesis development	Verilog/VHDL/C	XDMA Driver, peek/poke	Simulation, Virtual JTAG	HW Developer with intermediate FPGA experience
On-premise development for Alveo U200 using Vitis targetted for migration to F1	Vitis flow development using on-premise U200 platform targeted for migration to F1	C/C++/OpenCL, Verilog/VHDL (RTL)	OpenCL APIs and XRT	SW/HW Emulation, Simulation, GDB, JTAG (Chipscope)	SW or HW Developer with zero FPGA experience and on-premise U200 card
On-premise development for Alveo U200 using F1.A.1.4 shell	HDK flow for on-premise U200 card using F1.A.1.4 shell targetted for migration to F1	Verilog/VHDL	XDMA driver, peek/poke	Simulation, JTAG	HW Developer with advanced FPGA experience and on-premise U200 card

For on-premise development, SDAccel/Vitis/Vivado must have the correct license and use one of the supported tool versions.

FPGA Developer AMI

The FPGA Developer AMI is available on the AWS marketplace without a software charge and includes tools needed for developing FPGA Designs to run on AWS F1.

Given the large size of the FPGA used inside AWS F1 Instances, Xilinx tools work best with 32GiB Memory. z1d.xlarge/c5.4xlarge and z1d.2xlarge/c5.8xlarge instance types would provide the fastest execution time with 30GiB+ and 60GiB+ of memory respectively. Developers who want to save on cost, could start coding and run simulations on low-cost instances, like t2.2xlarge, and move to the aforementioned larger instances to run the synthesis of their acceleration code.

AWS marketplace offers multiple versions of the FPGA Developer AMI. The following section table describes the mapping of currently supported developer kit versions to AMI versions.

Xilinx tool support

Developer Kit Version	Tool Version Supported	Compatible FPGA Developer AMI Version
1.4.23+	2021.2	v1.12.X (Xilinx Vivado/Vitis 2021.2)
1.4.21+	2021.1	v1.11.X (Xilinx Vivado/Vitis 2021.1)
1.4.18+	2020.2	v1.10.X (Xilinx Vivado/Vitis 2020.2)
1.4.16+	2020.1	v1.9.0-v1.9.X (Xilinx Vivado/Vitis 2020.1)
1.4.13+	2019.2	v1.8.0-v1.8.X (Xilinx Vivado/Vitis 2019.2)
1.4.11+	2019.1	v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1)
1.4.8 - 1.4.15b	2018.3	v1.6.0-v1.6.X (Xilinx Vivado/SDx 2018.3)
1.4.3 - 1.4.15b	2018.2	v1.5.0-v1.5.X (Xilinx Vivado/SDx 2018.2)
⚠️ 1.3.7 - 1.4.15b	2017.4	v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) ⚠️

⚠️ Developer kit release v1.4.16 will remove support for Xilinx 2017.4, 2018.2, 2018.3 toolsets. While developer kit release v1.4.16 onwards will not support older Xilinx tools, you can still use them using HDK releases v1.4.15b or earlier. Please check out the latest v1.4.15b release tag from Github to use Xilinx 2017.4, 2018.2, 2018.3 toolsets.

For deprecation notices, please check the End of life announces

For software-defined development please look at the runtime compatibility table based on the Xilinx toolset in use: SDAccel or Vitis

End of life Announcements

Xilinx Tool version	State	Statement
2017.1	🚫 Deprecated on 09/01/2018	Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) reached end-of-life.
2017.4	🚫 Deprecated on 12/31/2021	Support for Xilinx 2017.4 toolsets was deprecated on 12/31/2021.
2020.1 and below	Discontinued on 02/2022	Removed the ability for customers to newly subscribe to 2020.1 and below AMI versions to remove exposure to CVE-2021-44228 as these versions of tools do not have patches from xilinx

Hardware Development Kit (HDK)

The HDK directory contains documentation, examples, simulation, build and AFI creation scripts to start building Amazon FPGA Images (AFI).
The HDK can be installed on any on-premises server or an EC2 instance. The developer kit is not required if you plan to use a pre-built AFI shared from another developer.

AWS Shells

With Amazon EC2 FPGA instances, each FPGA is divided into two partitions:

Shell (SH) – AWS platform logic implementing the FPGA external peripherals, PCIe, DRAM, and Interrupts.
Custom Logic (CL) – Custom acceleration logic created by an FPGA Developer.

At the end of the development process, combining the Shell and CL creates an Amazon FPGA Image (AFI) that can be loaded onto the Amazon EC2 FPGA Instances.

The following table provides the shells currently available to develop your CL with. Each shell provides specific interfaces and features and currently needs to be used with the Dev Kit branch listed in the table.

Shell Name	Shell Version	Dev Kit Branch	Description
F1 XDMA Shell	F1.X.1.4	master	Provides all the interfaces listed here, includes DMA
F1 Small Shell	F1.S.1.0	small_shell	Provides all the interfaces listed here. This shell does not include DMA engine and provides significant reduction in Shell resource usage.

For more details, check the FAQ

Software-defined Development Environment

The software-defined development environment allows customers to compile their C/C++/OpenCL code into the FPGA as kernels, and use OpenCL APIs to pass data to the FPGA. Software developers with no FPGA experience will find a familiar development experience that supercharges cloud applications.

In addition, this development environment allows for a mix of C/C++ and RTL accelerator designs into a C/C++ software based development environment. This method enables faster prototyping using C/C++ while supporting manual optimization of critical blocks within RTL. This approach is similar to optimizing time critical functions using software compiler optimization methods.

To get started with Xilinx SDAccel, review the Software-defined development environment readme. To get started with Xilinx Vitis, review the Vitis unified development environment readme.

Runtime Tools (SDK)

The SDK directory includes the runtime environment required to run on EC2 FPGA instances. It includes the drivers and tools to manage the AFIs that are loaded on the FPGA instance. The SDK isn't required during the AFI development process; it is only required once an AFI is loaded onto an EC2 FPGA instance. The following sdk resources are provided:

Linux Kernel Drivers - The developer kit includes three drivers:
- XDMA Driver - DMA interface to/from HDK accelerators.
FPGA Libraries - APIs used by C/C++ host applications.
FPGA Management Tools - AFI management APIs for runtime loading/clearing FPGA image, gathering metrics and debug interface on the F1 instance.

Amazon EC2 F1 Platform Features

1-8 Xilinx UltraScale+ VU9P based FPGA slots
Per FPGA Slot, Interfaces available for Custom Logic(CL):
- One x16 PCIe Gen 3 Interface
- Four DDR4 RDIMM interfaces (72-bit with ECC, 16 GiB each; 64 GiB total)
- AXI4 protocol support on all interfaces
User-defined clock frequency driving all CL to Shell interfaces
Multiple free running auxiliary clocks
PCI-E endpoint presentation to Custom Logic(CL)
- Management PF (physical function)
- Application PF
Virtual JTAG, Virtual LED, Virtual DIP Switches
PCI-E interface between Shell(SH) and Custom Logic(CL).
- SH to CL inbound 512-bit AXI4 interface
- CL to SH outbound 512-bit AXI4 interface
- Multiple 32-bit AXI-Lite buses for register access, mapped to different PCIe BARs
- Maximum payload size set by the Shell
- Maximum read request size set by the Shell
- AXI4 error handling
DDR interface between SH and CL
- CL to SH 512-bit AXI4 interface
- 1 DDR controller implemented in the SH (always available)
- 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)

Getting Started

Getting familiar with AWS

If you have never used AWS before, we recommend you start with AWS getting started training, and focus on the basics of the AWS EC2 and AWS S3 services. Understanding the fundamentals of these services will make it easier to work with AWS F1 and the FPGA Developer Kit.

FPGA Image generation and EC2 F1 instances are supported in the us-east-1 (N. Virginia), us-west-2 (Oregon), eu-west-1 (Ireland) and us-gov-west-1 (GovCloud US) regions.

⚠️ NOTE: By default, your AWS Account will have an EC2 F1 Instance launch limit of 0. Before using F1 instances, you will have to open a Support Case to increase the EC2 Instance limits to allow launching F1 instances.

Setting up development environment for the first time

You have the choice to develop on AWS EC2 using the FPGA Developer AMI or on-premise.

ℹ️ INFO: We suggest starting with the FPGA Developer AMI with build instances on EC2 as it has Xilinx tools and licenses setup for you to be able to quickly get into development.

ℹ️ INFO: For on-premise development, you will need to have Xilinx tools and licenses available for you to use

Start a Build Instance first to start your development.

💡 TIP: This instance does not have to be an F1 instance. You only require an F1 instance to run your AFI's(Amazon FPGA Image) once you have gone through your design build and AFI creation steps.

ℹ️ INFO: If you need to follow GUI Development flows, please checkout our Developer Resources where we provide Step-By-Step guides to setting up a GUI Desktop.
Clone the FPGA Developer Kit on your instance. git clone https://github.com/aws/aws-fpga.git
Follow the quickstarts from the next section.

Quickstarts

Before you create your own AWS FPGA design, we recommend that you go through one of the step-by-step Quickstart guides:

Description	Quickstart	Next Steps
Software Defined Accelerator Development using Xilinx Vitis	Vitis hello_world Quickstart	60+ Vitis examples, Vitis Library Examples
Software Defined Accelerator Development using Xilinx SDAccel	SDAccel hello_world Quickstart	60+ SDAccel examples
Custom Hardware Development(HDK)	HDK hello_world Quickstart	CL to Shell and DRAM connectivity example, Virtual Ethernet Application using the Streaming Data Engine
IP Integrator/High Level Design(HLx)	IPI hello_world Quickstart	IPI GUI Examples

ℹ️ INFO: For more in-depth applications and examples of using High level synthesis, Vitis Libraries, App Notes and Workshops, please refer to our Example List

How Tos

How To	Description
Migrate Alveo U200 designs to F1 - Vitis	This application note shows the ease of migrating an Alveo U200 design to F1.
Migrate Alveo U200 designs to F1 - HDK	Path to migrate from U200 vivado design flow to F1 HDK flow using AWS provided shells.

Documentation Overview

Documentation is located throughout this developer kit and the table below consolidates a list of key documents to help developers find information:

Topic	Document Name	Description
AWS setup	Setup AWS CLI and S3 Bucket	Setup instructions for preparing for AFI creation
Developer Kit	RELEASE NOTES, Errata	Release notes and Errata for all developer kit features, excluding the shell
Developer Kit	Errata	Errata for all developer kit features, excluding the shell
F1 Shell	AWS Shell RELEASE NOTES	Release notes for F1 shell
F1 Shell	AWS Shell ERRATA	Errata for F1 shell
F1 Shell	AWS Shell Interface Specification	Shell-CL interface specification for HDK developers building AFI
F1 Shell - Timeout and AXI Protocol Protection	How to detect a shell timeout	The shell will terminate transactions after a time period or on an illegal transaction. This describes how to detect and gather data to help debug CL issues caused by timeouts.
Vitis	Debug Vitis Kernel	Instructions on debugging Vitis Kernel
Vitis	Create Runtime AMI	Instructions on creating a runtime AMI when using Xilinx Vitis
Vitis	XRT Instructions	Instructions on building, installing XRT with MPD daemon considerations for F1
SDAccel	Debug RTL Kernel	Instructions on debugging RTL Kernel with SDAccel
SDAccel	Create Runtime AMI	Instructions on creating a runtime AMI when using Xilinx SDAccel
HDK - Host Application	Programmer View	Host application to CL interface specification
HDK - CL Debug	Debug using Virtual JTAG	Debugging CL using Virtual JTAG (Chipscope)
HDK - Simulation	Simulating CL Designs	Shell-CL simulation specification
HDK - Driver	README	Describes the DMA driver (XDMA) used by HDK examples and includes a link to an installation guide
AFI	AFI Management SDK	CLI documentation for managing AFI on the F1 instance
AFI - EC2 CLI	copy_fpga_image, delete_fpga_image, describe_fpga_images, fpga_image_attributes	CLI documentation for administering AFIs
AFI - Creation Error Codes	create_fpga_image_error_codes	CLI documentation for managing AFIs
AFI - Power	FPGA Power, recovering from clock gating	Helps developers with understanding FPGA power usage, preventing power violations on the F1 instance and recovering from a clock gated slot.
On-premise Development	Tools, Licenses required for on-premise development	Guidance for developer wanting to develop AFIs from on-premises instead of using the FPGA Developer AMI
PCIe Peer-2-Peer	P2P	Guidance on using PCIe P2P
PCIe write combining	PCIe write combine	Documentation on PCIe write combining for performance improvement
Frequently asked questions	FAQ	Q/A are added based on developer feedback and common AWS forum questions

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aws-fpga's Issues

error in check_s3_bucket_policy.py

I try to run this script check_s3_bucket_policy.

check_s3_bucket_policy.py --dcp-bucket zahar-fpga --dcp-key dcp-hello-world/17_08_01-095118.Developer_CL.tar --logs-bucket zahar-fpga --logs-key logs-folder

to verify the bucket policy and get this error:

File "check_s3_bucket_policy.py", line 1440, in
num_errors += checker.check()
File "check_s3_bucket_policy.py", line 344, in check
self.check_user_policy()
File "check_s3_bucket_policy.py", line 293, in check_user_policy
statement = PolicyStatement(statement, self.user_account_arn)
File "check_s3_bucket_policy.py", line 53, in init
self.process_policy_statement(statement, principal)
File "check_s3_bucket_policy.py", line 83, in process_policy_statement
actions = statement['Action']
TypeError: string indices must be integers

I use the example policy with changes at folder and file names .
any idea what can make it?

TIMING strategy fix lost in 1.3.4 update

The fix from PR #353 seems to have been lost with the 1.3.4 update. Without it, my build crashes with strategy TIMING, just like before that PR.

In READMEs with examples consider using linkable headings instead of bullets

I found that linking to a doc page is sometimes not specific enough. Instead, I need to link to the exact example snippet.

Currently, the bullets are used. Switching to headings would provide anchors that can be linked.

For example on this page:

Make AFI public:

    $ aws ec2 --region us-east-1 modify-fpga-image-attribute --fpga-image-id afi-0e5361a69d2af203d --operation-type add --user-groups all
<...>

Make AFI public:

    $ aws ec2 --region us-east-1 modify-fpga-image-attribute --fpga-image-id afi-0e5361a69d2af203d --operation-type add --user-groups all
<...>

shell_v04151701 new_cl_template not up to date

The 'create_dcp_from_cl.tcl' refers to AWS Design files that no longer exist in the newer shell version.

Example designs using this shell version seem OK though, so can base designs on these for now.

SDK support

This is a template for SDK issues. Please edit this template to file SDK bugs or support requests

misleading/incorrect info on RTL_Simulating_CL_Designs.md

poke_pcis() is supposed to have .strb as a parameter, but it's missing.

xdma driver install failed

I've encountered a problem when installing xdma driver, the error said:

Can't read private key

and

modprobe: ERROR: could not insert 'xdma': Exec format error

as you can see in the following logs

I've also tried the command:

lsmod | grep xdma

and see nothing.

Could anyone help me to checkout the problem? Thanks!

here are the logs:

$ sudo make install all
Makefile:25: XVC_FLAGS: .
make -C /lib/modules/3.10.0-693.21.1.el7.x86_64/build M=/home/centos/aws-fpga/sdk/linux_kernel_drivers/xdma modules
make[1]: Entering directory /usr/src/kernels/3.10.0-693.21.1.el7.x86_64' /home/centos/aws-fpga/sdk/linux_kernel_drivers/xdma/Makefile:25: XVC_FLAGS: . Building modules, stage 2. /home/centos/aws-fpga/sdk/linux_kernel_drivers/xdma/Makefile:25: XVC_FLAGS: . MODPOST 1 modules make[1]: Leaving directory /usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
make -C /lib/modules/3.10.0-693.21.1.el7.x86_64/build M=/home/centos/aws-fpga/sdk/linux_kernel_drivers/xdma modules_install
make[1]: Entering directory /usr/src/kernels/3.10.0-693.21.1.el7.x86_64' INSTALL /home/centos/aws-fpga/sdk/linux_kernel_drivers/xdma/xdma.ko Can't read private key DEPMOD 3.10.0-693.21.1.el7.x86_64 make[1]: Leaving directory /usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
depmod -a
install -m 644 10-xdma.rules /etc/udev/rules.d
rmmod -s xdma || true
modprobe xdma
modprobe: ERROR: could not insert 'xdma': Exec format error
make: [install] Error 1 (ignored)
make: `all' is up to date.

Link to Programmer_View is wrong

In both README.md and AWS_Fpga_Pcie_Memory_Map.md the URL is wrong: instead Programmers_View.md it should be Programmer_View.md

create_sdaccel_afi.sh Usage advertises non-existent debug flag

info_msg "USAGE: $script_name [-d|-debug]

Why S3 bucket and its related things are required for awsxclbin

I wonder why S3 things are required to prepare awsxclbin.

When I try to prepare awsxclbin from xclbin using create_sdaccel_afi.sh, it requires s3_bucket, s3_dcps_key, s3_log_key and so.

These are not explained in this README file.

Above all, why ASW F1 doe not use something automatic conversion internally when xclbin file is given for SDAccel/OpenCL application runs?

AWS F1 instance for SDAccel requires too many additional prerequisites, which are not common at local machine.

Any help could make me save time and money and efforts.

fatal error: xcldma/include/xdma-ioctl.h: No such file or directory

fatal error: xcldma/include/xdma-ioctl.h: No such file or directory
fatal error: baremetal/mgmt/mgmt-ioctl.h: No such file or directory
when I run makefile in sdk/SDAccel/userspace/src,the report is fatal error,
I could not find these files in github.

source sdaccel.sh fails on latest master

/home/centos/aws-fpga/sdk/linux_kernel_drivers/xocl/xocl_bo.c:55:9: error: too many arguments to function ‘drm_mm_insert_node_generic’
return drm_mm_insert_node_generic(mm, node, size, PAGE_SIZE, 0, 0, 0);

HDK bug

Release version

Expected Behavior

Actual Behavior

Steps to reproduce

It's better to change “data transferred / execution time” to "execution time / data transferred" in SDAccel_Guide_AWS_F1.md.

It's better to change “data transferred / execution time” to "execution time / data transferred" from the context in SDAccel_Guide_AWS_F1.md.

hdk_version.txt not updated

Should now read 1.2.1?

Hardware Emulation but hardware fails

Mu custom RTL in the system created using the SDAccel RTL Kernel Wizard 2017.1 works correctly in the hardware emulation mode. But when I run on the AWS F1 instance, the program hangs up as soon as the input is sent to the FPGA (no response back).

Any input on what could be the potential issue?

SDK feature

@aws/f1-fpga-software-development-kit

This is template for SDK feature request. Please edit this template and add detailed description of the issue. Any supporting documentation can also be attached.

Release version

Feature request

How can I get the reports after running on F1

After running the hardware emulation of the Xilinx example helloworld_ocl with $AWS_PLARTFORM_4DDR_DEBUG, it would generates the profile reports. While after running in the FPGA, there's no reports generated. I have tried to modify the makefile rules.mk to add a --debug option for xocc, which does not help. How can I get these reports for the hardware running?

HelloWorld Example

Could you make the Hello World example available in Europe Ireland as well, please?

hdk_setup.sh fails on CentOS image

The source hdk_setup.sh steps fails when run on the CentOS instance.

 ___ ___  ___   _     ___  _____   __    _   __  __ ___
| __| _ \/ __| /_\   |   \| __\ \ / /   /_\ |  \/  |_ _|
| _||  _/ (_ |/ _ \  | |) | _| \ V /   / _ \| |\/| || |
|_| |_|  \___/_/ \_\ |___/|___| \_/   /_/ \_\_|  |_|___|
Readme:          /home/centos/src/README.md
GUI Setup Steps: /home/centos/src/GUI_README.md
Xilinx Tools:    /opt/Xilinx/
[centos@ip-172-31-29-66 aws-fpga]$ source hdk_setup.sh
AWS FPGA: hdk_setup.sh script will (i) check if Xilinx's vivado is installed, (ii) set up key environment variables HDK_*, and (iii) prepare DRAM controller and PCIe IP modules if they are not already available in your directory.
AWS FPGA: Checking for vivado install:
AWS FPGA: Vivado check successed
AWS FPGA: Setting up environment variables
AWS FPGA: Done setting environment variables.
AWS FPGA: ATTENTION: Don't forget to change the CL_DIR variable for the directory of your Custom Logic.
DDR4 model files in /home/centos/aws-fpga/hdk/common/verif/models/ddr4_model/ do NOT exist. Running model creation step.
This could take 5-10 minutes, please be patient!
NOTE: This step requires having Xilinx Vivado installed and running Licensing Manager

****** Vivado v2016.3 (64-bit)
  **** SW Build 1682563 on Mon Oct 10 19:07:26 MDT 2016
  **** IP Build 1681267 on Mon Oct 10 21:28:31 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script '/opt/Xilinx/Vivado/2016.3/scripts/init.tcl'
80 Beta devices matching pattern found, 80 enabled.
source /home/centos/aws-fpga/hdk/common/verif/scripts/init.tcl
# set_msg_config -severity INFO -suppress
# set_msg_config -severity STATUS -suppress
# set_msg_config -severity WARNING -suppress
CRITICAL WARNING: [Common 17-1355] You are suppressing all messages of type 'WARNING'. You may potentially disregard important DRC, CDC, and implementation messages that can negatively impact your design.  If this is not desired, please run 'reset_msg_config -suppress -severity {WARNING}' to undo this change.
# set_msg_config -string {exportsim} -suppress
# set_msg_config -string {IP_Flow} -suppress
# create_project -force tmp_ddr ./tmp -part xcvu9p-flgb2104-2-i-es1
# add_files -norecurse $::env(HDK_COMMON_DIR)/shell_latest/design/ip/ddr4_core/ddr4_core.xci
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.3/data/ip'.
add_files: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1346.457 ; gain = 235.266 ; free physical = 65 ; free virtual = 482
# export_ip_user_files -of_objects  [get_files  $::env(HDK_COMMON_DIR)/shell_latest/design/ip/ddr4_core/ddr4_core.xci] -force -quiet
# open_example_project -force -dir ./tmp/tmp_ddr_ex [get_ips  ddr4_core]
INFO: [IP_Flow 19-1686] Generating 'Examples' target for IP 'ddr4_core'...
INFO: [Device 21-403] Loading part xcvu9p-flgb2104-2-i-es1
/opt/Xilinx/Vivado/2016.3/bin/loader: line 164: 15248 Killed                  "$RDI_PROG" "$@"
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/arch_defines.v’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/arch_package.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_model.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_sdram_model_wrapper.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/interface.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/MemoryArray.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/proj_package.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/StateTableCore.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/StateTable.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/timing_tasks.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_bi_delay.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_db_delay_model.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_db_dly_dir.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_dimm.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_dir_detect.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_rank.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_rcd_model.sv’: No such file or directory
cp: cannot stat ‘tmp/tmp_ddr_ex/ddr4_core_ex/imports/ddr4_rdimm_wrapper.sv’: No such file or directory
Done with model creation step. Cleaning up temporary files.
AWS FPGA: Done with AWS HDK setup.

Please don't remove the line below

@aws/fpga-user

Creating a sample issue

sample only

HDK feature

@aws/fpga-user

This is a template for new HDK feature requests. Please edit this template and add detailed description of the feature being requested. Any supporting documentation can also be attached.

Release version

Feature request

Is there any can accelerate synthesize

It took too long to synthesize every time (More than 1 hour), is there any suggestion to accelerate synthesize?

sdaccel_setup.sh fails on aws fpga dev ami

In the Ireland region, after starting a c4.4xlarge with the ami FPGA Developer AMI - 1.4.0 - pre8-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-0335b86e84e820e8d.4 (ami-c6be8bbf), when running sdaccel_setup.sh, I get an error like:

install: cannot stat ‘/opt/Xilinx/SDx/2017.4.op/lib/lnx64.o/libstdc++.so*’: No such file or directory
make: *** [install] Error 1
ERROR: Install of SDAccel runtime FAILED

In the eu-west-1 region, with ami FPGA Developer AMI - 1.4.0 - pre8-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-0335b86e84e820e8d.4 (ami-f7ba3988), it gives the same error.

Maybe there is a new version of the AMI, and the script needs updating?

Full log:

[centos@ip-172-30-1-66 ~]$ git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR
Cloning into '/home/centos/src/project_data/aws-fpga'...
remote: Counting objects: 5550, done.
remote: Compressing objects: 100% (362/362), done.
remote: Total 5550 (delta 131), reused 324 (delta 94), pack-reused 5065
Receiving objects: 100% (5550/5550), 224.20 MiB | 27.06 MiB/s, done.
Resolving deltas: 100% (2779/2779), done.
Checking out files: 100% (1201/1201), done.
[centos@ip-172-30-1-66 ~]$ cd $AWS_FPGA_REPO_DIR
[centos@ip-172-30-1-66 aws-fpga]$ source sdaccel_setup.sh
INFO: Setting up environment variables
DEBUG: AWS_FPGA_REPO_DIR=/home/centos/src/project_data/aws-fpga
INFO: Sourcing sdk_setup.sh
INFO: Setting up environment variables
DEBUG: AWS_FPGA_REPO_DIR=/home/centos/src/project_data/aws-fpga
Entering /home/centos/src/project_data/aws-fpga/sdk/userspace/utils
rm -f *.o *.a ../lib/libutils.a
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../include -I/usr/include   -c -o io.o io.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../include -I/usr/include   -c -o log.o log.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../include -I/usr/include   -c -o logger-kmsg.o logger-kmsg.c
mkdir -p ../lib
ar rcs ../lib/libutils.a io.o log.o logger-kmsg.o
Entering /home/centos/src/project_data/aws-fpga/sdk/userspace/fpga_libs/fpga_pci
rm -f *.o ../../lib/libfpga_pci.a
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../../include -I/usr/include   -c -o fpga_pci.o fpga_pci.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../../include -I/usr/include   -c -o fpga_pci_sysfs.o fpga_pci_sysfs.c
mkdir -p ../../lib
ar rcs ../../lib/libfpga_pci.a fpga_pci.o fpga_pci_sysfs.o
Entering /home/centos/src/project_data/aws-fpga/sdk/userspace/fpga_libs/fpga_mgmt
rm -f *.o ../../lib/libfpga_mgmt.a ../../lib/so/libfpga_mgmt.so.1.0.0
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../../include -I/usr/include   -c -o fpga_mgmt.o fpga_mgmt.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../../include -I/usr/include   -c -o fpga_mgmt_cmd.o fpga_mgmt_cmd.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I. -I../../include -I/usr/include   -c -o fpga_hal_mbox.o fpga_hal_mbox.c
mkdir -p ../../lib
for library in ../../lib/libfpga_pci.a ../../lib/libutils.a; do ar -x $library; done
ar rcs ../../lib/libfpga_mgmt.a *.o
mkdir -p ../../lib/so
cc -o ../../lib/so/libfpga_mgmt.so.1.0.0 -shared fpga_mgmt.o fpga_mgmt_cmd.o fpga_hal_mbox.o -Wl,-soname,libfpga_mgmt.so.1 -Wl,--whole-archive ../../lib/libfpga_pci.a ../../lib/libutils.a -Wl,--no-whole-archive -lrt -lpthread
ln -sf libfpga_mgmt.so.1.0.0 ../../lib/so/libfpga_mgmt.so
Entering /home/centos/src/project_data/aws-fpga/sdk/userspace/fpga_mgmt_tools/src
rm -f *.o *.a fpga-local-cmd static-fpga-local-cmd
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g  -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I../../include/hal -I../../include -I../. -I.   -c -o fpga_local_cmd.o fpga_local_cmd.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g  -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I../../include/hal -I../../include -I../. -I.   -c -o fpga_local_cmd_parse.o fpga_local_cmd_parse.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g  -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I../../include/hal -I../../include -I../. -I.   -c -o virtual_jtag_pcie.o virtual_jtag_pcie.c
cc -DCONFIG_LOGLEVEL=0 -DFPGA_PCI_BARS_MAX=64 -g  -Wall -Werror -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes -I../../include/hal -I../../include -I../. -I.   -c -o virtual_jtag_server.o virtual_jtag_server.c
cc -o fpga-local-cmd fpga_local_cmd.o fpga_local_cmd_parse.o virtual_jtag_pcie.o virtual_jtag_server.o -L../../lib/so -lfpga_mgmt
cc -o static-fpga-local-cmd fpga_local_cmd.o fpga_local_cmd_parse.o virtual_jtag_pcie.o virtual_jtag_server.o -L../../lib -lfpga_mgmt -lrt -lpthread
Build complete.

Root privileges are required to install. You may be asked for your password...
Executing as root...

AWS FPGA: Copying Amazon FPGA Image (AFI) Management Tools to /usr/bin
AWS FPGA: Installing shared library to /usr/local/lib64
	libfpga_mgmt.so.1 (libc6,x86-64) => /usr/local/lib64/libfpga_mgmt.so.1
AWS FPGA: Done with Amazon FPGA Image (AFI) Management Tools install.
Done with SDK install.
INFO: sdk_setup.sh PASSED
INFO: Updating Xilinx SDAccel Examples
Submodule 'SDAccel/examples/xilinx' (https://github.com/Xilinx/SDAccel_Examples.git) registered for path 'SDAccel/examples/xilinx'
Cloning into 'SDAccel/examples/xilinx'...
remote: Counting objects: 18786, done.
remote: Compressing objects: 100% (84/84), done.
remote: Total 18786 (delta 41), reused 48 (delta 20), pack-reused 18682
Receiving objects: 100% (18786/18786), 342.15 MiB | 27.55 MiB/s, done.
Resolving deltas: 100% (13627/13627), done.
Submodule path 'SDAccel/examples/xilinx': checked out '51416734fd694773a2ab4991f027e5c78e09c9a8'
INFO: XILINX_SDX is already set to /opt/Xilinx/SDx/2017.4.op
HTTP/1.1 301 Moved Permanently
Server: CloudFront
Date: Sun, 13 May 2018 13:41:22 GMT
Content-Type: text/html
Content-Length: 183
Connection: keep-alive
Location: https://www.amazon.com/
X-Cache: Redirect from cloudfront
Via: 1.1 6024046f65540b3a21a6778b84867fbe.cloudfront.net (CloudFront)
X-Amz-Cf-Id: ZHNVi-tSehHtH_435s787-CPqlCgkoRJbe0EZUQMxAsVrqdd2TVHDQ==

INFO: Internet Access OK
INFO: Checking ICD is installed
INFO: Found 'libxilinxopencl.so
INFO: SDK DSA hasn't been downloaded yet.
INFO: Downloading latest SDK DSA checkpoint from aws-fpga-hdk-resources/SDAccel/dsa_v0911_shell_v071417d3/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0.dsa
INFO: AWS Platform: 4DDR is up-to-date
INFO: SDK DSA hasn't been downloaded yet.
INFO: Downloading latest SDK DSA checkpoint from aws-fpga-hdk-resources/SDAccel/dsa_v11517_shell_v071417d3/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0.dsa
INFO: AWS Platform: 1DDR is up-to-date
INFO: SDK DSA hasn't been downloaded yet.
INFO: Downloading latest SDK DSA checkpoint from aws-fpga-hdk-resources/SDAccel/dsa_v11517_shell_v071417d3/xilinx_aws-vu9p-f1_4ddr-xpr-2pr-debug_4_0/xilinx_aws-vu9p-f1_4ddr-xpr-2pr-debug_4_0.dsa
INFO: AWS Platform: 4DDR RTL Kernel is up-to-date
INFO: Building SDAccel runtime
SDK_DIR = /home/centos/src/project_data/aws-fpga/sdk
SDACCEL_DIR = /home/centos/src/project_data/aws-fpga/SDAccel
XILINX_SDX = /opt/Xilinx/SDx/2017.4.op
make -C /home/centos/src/project_data/aws-fpga/SDAccel/userspace/src debug=1 ec2=1
make[1]: Entering directory `/home/centos/src/project_data/aws-fpga/SDAccel/userspace/src'
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c perf.cpp -o perf.o
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c -MM perf.cpp -o  perf.d
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c memorymanager.cpp -o memorymanager.o
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c -MM memorymanager.cpp -o  memorymanager.d
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c shim.cpp -o shim.o
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c -MM shim.cpp -o  shim.d
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c xclbin.cpp -o xclbin.o
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c -MM xclbin.cpp -o  xclbin.d
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c debug.cpp -o debug.o
g++ -Werror -std=c++11 -Werror -std=c++11 -DXCLHAL_MAJOR_VER=1 -DXCLHAL_MINOR_VER=1 -I../include -I/home/centos/src/project_data/aws-fpga/sdk/userspace/include -I/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers -fpic -fvisibility=hidden -lrt -g -DDEBUG   -c -MM debug.cpp -o  debug.d
ar rcv -o libawsxcldrv.a  perf.o   memorymanager.o   shim.o   xclbin.o   debug.o
a - perf.o
a - memorymanager.o
a - shim.o
a - xclbin.o
a - debug.o
g++ -shared -o libawsxcldrv.so  perf.o   memorymanager.o   shim.o   xclbin.o   debug.o  -L/home/centos/src/project_data/aws-fpga/sdk/userspace/lib -lfpga_mgmt
make[1]: Leaving directory `/home/centos/src/project_data/aws-fpga/SDAccel/userspace/src'
make -C /home/centos/src/project_data/aws-fpga/SDAccel/tools/awssak debug=1 ec2=1
make[1]: Entering directory `/home/centos/src/project_data/aws-fpga/SDAccel/tools/awssak'
g++ -Wall -Werror -std=c++11 -I../../include -I/home/centos/src/project_data/aws-fpga/SDAccel/userspace/include -g -D_DEBUG   -c main.cpp -o main.o
g++ -Wall -Werror -std=c++11 -I../../include -I/home/centos/src/project_data/aws-fpga/SDAccel/userspace/include -g -D_DEBUG   -c -MM main.cpp -o  main.d
g++ -o xbsak  main.o /home/centos/src/project_data/aws-fpga/SDAccel/userspace/src/libawsxcldrv.a -L/home/centos/src/project_data/aws-fpga/sdk/userspace/lib -lfpga_mgmt -lrt
make[1]: Leaving directory `/home/centos/src/project_data/aws-fpga/SDAccel/tools/awssak'
make -C /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma
make[1]: Entering directory `/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma'
Makefile:25: XVC_FLAGS: .
make -C /lib/modules/3.10.0-693.21.1.el7.x86_64/build M=/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma modules
make[2]: Entering directory `/usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/Makefile:25: XVC_FLAGS: .
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/libxdma.o
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/xdma_cdev.o
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/cdev_ctrl.o
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/cdev_events.o
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/cdev_sgdma.o
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/cdev_xvc.o
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/cdev_bypass.o
  CC [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/xdma_mod.o
  LD [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/xdma.o
  Building modules, stage 2.
/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/Makefile:25: XVC_FLAGS: .
  MODPOST 1 modules
  CC      /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/xdma.mod.o
  LD [M]  /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/xdma.ko
make[2]: Leaving directory `/usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
make[1]: Leaving directory `/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma'
INFO: Installing SDAccel runtime
SDK_DIR = /home/centos/src/project_data/aws-fpga/sdk
SDACCEL_DIR = /home/centos/src/project_data/aws-fpga/SDAccel
XILINX_SDX = /opt/Xilinx/SDx/2017.4.op
make -C /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma install
make[1]: Entering directory `/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma'
Makefile:25: XVC_FLAGS: .
make -C /lib/modules/3.10.0-693.21.1.el7.x86_64/build M=/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma modules
make[2]: Entering directory `/usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/Makefile:25: XVC_FLAGS: .
  Building modules, stage 2.
/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/Makefile:25: XVC_FLAGS: .
  MODPOST 1 modules
make[2]: Leaving directory `/usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
make -C /lib/modules/3.10.0-693.21.1.el7.x86_64/build M=/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma modules_install
make[2]: Entering directory `/usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
  INSTALL /home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma/xdma.ko
Can't read private key
  DEPMOD  3.10.0-693.21.1.el7.x86_64
make[2]: Leaving directory `/usr/src/kernels/3.10.0-693.21.1.el7.x86_64'
depmod -a
install -m 644 10-xdma.rules /etc/udev/rules.d
rmmod -s xdma || true
modprobe xdma
make[1]: Leaving directory `/home/centos/src/project_data/aws-fpga/sdk/linux_kernel_drivers/xdma'
install -d /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/platforms/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0/driver
install -d /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/bin
install -d /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/lib/x86_64
install -m 755 /home/centos/src/project_data/aws-fpga/SDAccel/userspace/src/libawsxcldrv.so /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/platforms/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0/driver
install -m 755 /home/centos/src/project_data/aws-fpga/SDAccel/tools/awssak/xbsak /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/bin
install -m 755 /opt/Xilinx/SDx/2017.4.op/runtime/bin/xclbincat /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/bin
install -m 755 /opt/Xilinx/SDx/2017.4.op/runtime/bin/xclbinsplit /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/bin
#install -m 755 /opt/Xilinx/SDx/2017.4.op/lib/lnx64.o/libxilinxopencl.so /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/lib/x86_64
install -m 755 /home/centos/src/project_data/aws-fpga/SDAccel/aws_platform/libxilinxopencl.so /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/lib/x86_64
install -m 755 /opt/Xilinx/SDx/2017.4.op/lib/lnx64.o/libstdc++.so* /opt/Xilinx/SDx/2017.1.rte.1ddr/runtime/lib/x86_64
install: cannot stat ‘/opt/Xilinx/SDx/2017.4.op/lib/lnx64.o/libstdc++.so*’: No such file or directory
make: *** [install] Error 1
ERROR: Install of SDAccel runtime FAILED

@fpga-user

@aws/fpga-user

This is test for a sample issue creation

Release version

1.0.0

Expected Behavior

TEST

Actual Behavior

TEST

Steps to reproduce

TEST

Once fpga goes into error, it can never be recovered.. even after stop and start of instance

I had the same awsxclbin working. But somehow it went into error and now i cannt recover it.

[centos@ip-10-172-2-23 FFmpeg-n3.3.2]$ sudo fpga-clear-local-image -S 0
AFI 0 none cleared 1 ok 0 0x071417d3
AFIDEVICE 0 0x1d0f 0x1042 0000:00:1d.0
[centos@ip-10-172-2-23 FFmpeg-n3.3.2]$ sudo ./ffmpeg -f rawvideo -s:v 1920x1080 -i ~/Kimono1_1920x1080_24.yuv -c:v NGCVP9 -g 0 -idr-period 120 -b:v 3M -f rawvideo ~/a.vp9
ffmpeg version 3.3.2 Copyright (c) 2000-2017 the FFmpeg developers
built with gcc 4.8.5 (GCC) 20150623 (Red Hat 4.8.5-28)
configuration: --enable-libxmaapi
libavutil 55. 58.100 / 55. 58.100
libavcodec 57. 89.100 / 57. 89.100
libavformat 57. 71.100 / 57. 71.100
libavdevice 57. 6.100 / 57. 6.100
libavfilter 6. 82.100 / 6. 82.100
libswscale 4. 6.100 / 4. 6.100
libswresample 2. 7.100 / 2. 7.100
calling xma cfg init
Loading 'abr_cfg.yaml':
Using HAL layer
[0]user:0x1042:0x7:[???:??:0]
xclProbe found 1 FPGA slots with xocl driver running
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD0
WARNING: AwsXcl isGood: invalid user handle.
WARNING: xclOpen Handle check failed
[0]user:0xf000:0x1d51:[???:??:0]
device[0].user_instance : 0
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD0
WARNING: AwsXcl isGood: invalid user handle.
ERROR: xclOpen Handle check failed
get_device_list xclOpen handle = (nil)
xclGetDeviceInfo2 failed for device id: 0, rc=-1
xma_initialize failed: rc = -1

Typo in hdk/common/verif/include/sh_dpi_tasks.svh

There is a typo in the peek_bar1 and peek_sda tasks. The peek_ocl task is correct. See patch below:

@@ -430,7 +440,7 @@ end
              output logic [63:0] data,
              input logic [5:0] id = 6'h0);
        logic [63:0] tmp;
-       `SLOT_MACRO_TASK(peek(.addr(addr), .data(data), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_SDA)))
+       `SLOT_MACRO_TASK(peek(.addr(addr), .data(tmp), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_SDA)))
        data = tmp[31:0];
    endtask

@@ -468,7 +478,7 @@ end
              output logic [63:0] data,
              input logic [5:0] id = 6'h0);
        logic [63:0] tmp;
-       `SLOT_MACRO_TASK(peek(.addr(addr), .data(data), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_BAR1)))
+       `SLOT_MACRO_TASK(peek(.addr(addr), .data(tmp), .id(id), .size(DataSize::UINT32), .intf(AxiPort::PORT_BAR1)))
        data = tmp[31:0];
    endtask

HDK Bug

@aws/f1-fpga-hardware-development-kit

This is a template for filing HDK bugs. Please edit this template and fill out as many details as possible.

Release version

Expected Behavior

Actual Behavior

Steps to reproduce

Vector Addition in OpenCL: need help

"Vector addition" (my own) causes segmentation fault on AWS.

I prepared "vector addition" example, which was tested on local machine with KCU1500 board.
I moved the design to ASW F1 @ N. Virginia and then did as follows.

Set AWS FPGA environment
$ source aws-fpga/sdaccel_setup.sh
Prepared host program and xclbin for VCU1525
... as you know it took pretty long time ...
... it generates xclbin file someting like krnl_vadd.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin
Got root
root$ sudo su
Set run-time environment
root$ source /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh
Run the host program
root$ ./host
It ends up with following message

[0]user:0xf010:0x1d51:[xocl:2017.4.5:128]
xclProbe found 1 FPGA slots with xocl driver running
INFO: Importing xclbin/krnl_vadd.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin
INFO: Loaded file
Segmentation fault (core dumped)

Do I need awsxclbin instead of xclbin?

Create_Runtime_AMI.md is broken

Any issues related to HDK or SDK should be filed on FPGA development Forum.

The AWS FPGA Development User Forum is the first place to go to post questions, suggestions and important announcements.

Section 2, Copy required Xilinx SDAccel Runtime Libraries to the Instance and Reboot your Runtime Instance.

The instruction is broken, first, it should be $XILINX_SDX, not $XIILNX_SDX. Second, those binary files to be copied have be moved around in the newest developer AMI.

Maybe just ask people to copy the rte.dyn directory?

Asking for more specific example for generating AFI

Are anyone who can give more specific example for generating AFI.
I tried to generate AFI from xclbin. To do so, first I prepared S3 bucket, but it does occurs error; Setup CLI and Create S3 Bucket.

What I'm looking for is a real example for this.

   $ aws s3 mb s3://<bucket-name> --region us-east-1  # Create an S3 bucket (choose a unique bucket name)
    $ aws s3 mb s3://<bucket-name>/<dcp-folder-name>   # Create folder for your tarball files
    $ touch FILES_GO_HERE.txt                          # Create a temp file
    $ aws s3 cp FILES_GO_HERE.txt s3://<bucket-name>/<dcp-folder-name>/  # Which creates the folder on S3

What I did,

[centos@AWS] aws s3 mb s3://fpga-aws --region us-east-1
make_bucket: fpga-aws
[centos@AWS] aws s3 mb s3://fpga-aws/dcp
make_bucket failed: s3://fpga-aws/dcp Could not connect to the endpoint URL: "https://fpga-aws.s3.us-east-1c.amazonaws.com/"
[centos@AWS]

open_checkpoint' (SH_CL_BB_routed.dcp) failed

I want to compile the cl_hello_world example on my local matchine. I have installed hdk and aws_cli tools. When I run command ./aws_build_dcp_from_cl.sh, the post_synth.dcp can be generated. But the process would be terminated. The log is:

#puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
AWS FPGA: (18:09:39) writing post synth checkpoint.
# write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.04 . Memory (MB): peak = 
3156.297 ; gain = 0.000 ; free physical = 28519 ; free virtual = 37673
# close_project
# puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Optimizing design.";
AWS FPGA: (18:09:43) Optimizing design.
# puts "AWS FPGA: Implementation step -Combining Shell and CL design checkpoints";
AWS FPGA: Implementation step -Combining Shell and CL design checkpoints
# open_checkpoint $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
resize_pblock: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4077.734 ; gain = 
41.906 ; free physical = 26960 ; free virtual = 36605
create_generated_clock: Time (s): cpu = 00:00:34 ; elapsed = 00:00:11 . Memory (MB): peak = 4658.668 
; gain = 558.809 ; free physical = 26519 ; free virtual = 36164
Read XDEF File: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 5303.051 ; gain = 
0.000 ; free physical = 26122 ; free virtual = 35767
Finished XDEF File Restore: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 
5303.051 ; gain = 0.000 ; free physical = 26119 ; free virtual = 35764

ERROR: [Designutils 20-1448] Failed to read archive '/home/work/aws_fpga/aws-
fpga/hdk/cl/examples/cl_hello_world/build/scripts/.Xil/Vivado-21269-SDAccel/dcp4/top_sp.incr': input 
stream error. The archive does not contain an expected string or is corrupted.
open_checkpoint: Time (s): cpu = 00:02:12 ; elapsed = 00:01:38 . Memory (MB): peak = 5303.055 ; gain 
= 2146.750 ; free physical = 26570 ; free virtual = 35723
ERROR: [Common 17-39] 'open_checkpoint' failed due to earlier errors.

    while executing
 "open_checkpoint $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp"
    (file "create_dcp_from_cl.tcl" line 283)

I have checked that there is no "Vivado-21269* " in directory ".Xil". I don't know what causes this problem and how to resolve it!

TIMING strategy fix lost in 1.3.6 update

The fix from PR #353 seems to have been lost with the 1.3.6 update. Without it, my build crashes with strategy TIMING, just like before that PR. Same as issue #376 from 1.3.4.

sv_fpga_start_buffer_to_cl and sv_fpga_start_cl_to_buffer for unprintable chars

I have been using sv_fpga_start_buffer_to_cl and sv_fpga_start_cl_to_buffer in simulation.
These functions only work under the assumption that there is no "\0" char in the string.
When using raw data values as input with a '0' value in the string all subsequent characters are set to 0 and hence have incorrect input passed into the design in simulation.

test

HDK Support

This is a template for HDK issues. Please edit this template to file HDK bugs or support requests

SDAccel - helloworld_ocl

I am getting some errors when I try to program/run the helloworld_ocl example on the recent upgrade. I am using AMI 1.4.0 and v1.3.7 (aws-repo). It seems a driver (userspace) issue, any thoughts?

Device/Slot[0] (/dev/xdma0, 0:0:1d.0)
xclProbe found 1 FPGA slots with XDMA driver running
opendir: Path /sys/bus/pci/devices/0000:00:1d.0/drm does not exist or could not be read: No such file or directory
[0]user:0x1042:0x7:[xdma:2017.1.47:65535]
xclProbe found 1 FPGA slots with xocl driver running
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD65535
WARNING: AwsXcl isGood: invalid user handle.
WARNING: xclOpen Handle check failed
opendir: Path /sys/bus/pci/devices/0000:00:1d.0/drm does not exist or could not be read: No such file or directory
[0]user:0x1042:0x7:[xdma:2017.1.47:65535]
device[0].user_instance : 65535
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD65535
WARNING: AwsXcl isGood: invalid user handle.
ERROR: xclOpen Handle check failed
ERROR: Device setup failed
Device/Slot[0] (/dev/xdma0, 0:0:1d.0)
xclProbe found 1 FPGA slots with XDMA driver running
opendir: Path /sys/bus/pci/devices/0000:00:1d.0/drm does not exist or could not be read: No such file or directory
[0]user:0x1042:0x7:[xdma:2017.1.47:65535]
xclProbe found 1 FPGA slots with xocl driver running
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD65535
WARNING: AwsXcl isGood: invalid user handle.
WARNING: xclOpen Handle check failed
opendir: Path /sys/bus/pci/devices/0000:00:1d.0/drm does not exist or could not be read: No such file or directory
[0]user:0x1042:0x7:[xdma:2017.1.47:65535]
device[0].user_instance : 65535
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD65535
WARNING: AwsXcl isGood: invalid user handle.
ERROR: xclOpen Handle check failed
ERROR: Device setup failed
Device/Slot[0] (/dev/xdma0, 0:0:1d.0)
xclProbe found 1 FPGA slots with XDMA driver running
opendir: Path /sys/bus/pci/devices/0000:00:1d.0/drm does not exist or could not be read: No such file or directory
[0]user:0x1042:0x7:[xdma:2017.1.47:65535]
xclProbe found 1 FPGA slots with xocl driver running
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD65535
WARNING: AwsXcl isGood: invalid user handle.
WARNING: xclOpen Handle check failed
opendir: Path /sys/bus/pci/devices/0000:00:1d.0/drm does not exist or could not be read: No such file or directory
[0]user:0x1042:0x7:[xdma:2017.1.47:65535]
device[0].user_instance : 65535
WARNING: AwsXcl - Cannot open userPF: /dev/dri/renderD65535
WARNING: AwsXcl isGood: invalid user handle.
ERROR: xclOpen Handle check failed
ERROR: Device setup failed
Error: Failed to find Xilinx platform

SDK bug

@aws/f1-fpga-software-development-kit

This is a template for SDK bugs. Please edit this template and fill out as many details as possible.

Release version

Expected Behavior

Actual Behavior

Steps to reproduce

source sdaccel_setup.sh fails

CC [M] /aws-fpga/sdk/linux_kernel_drivers/xocl/xocl_sysfs.o
In file included from /home/gsneha/aws-fpga/sdk/linux_kernel_drivers/xocl/xocl_sysfs.c:19:0:
/aws-fpga/sdk/linux_kernel_drivers/xocl/xocl_drv.h:27:25: fatal error: drm/drm_gem.h: No such file or directory
#include <drm/drm_gem.h>
^
compilation terminated.
make[3]: *** [/aws-fpga/sdk/linux_kernel_drivers/xocl/xocl_sysfs.o] Error 1
make[2]: *** [module/aws-fpga/sdk/linux_kernel_drivers/xocl] Error 2
make[2]: Leaving directory /usr/src/linux-headers-3.2.0-29-generic' make[1]: *** [all] Error 2 make[1]: Leaving directory /aws-fpga/sdk/linux_kernel_drivers/xocl'
make: *** [all] Error 2
ERROR: Build of SDAccel runtime FAILED

On-Premises Instructions link is broken

The page https://github.com/aws/aws-fpga/blob/master/SDAccel/README.md#iss with the link to https://github.com/aws/aws-fpga/blob/hdk/docs/on_premise_licensing_help.md i sbroken

pull request for CL scripts for alternative development tools that support F1 platform?

Hello,

It's more of a question rather than an issue. I'm posting it here because it's specifically related to this repository rather than F1/HDK in general.

Are the maintainers okay with accepting a pull request for CL scripts that enable workflow through an alternative FPGA development tool (which has support for AWS F1 platform).

The development tool is Visual System Integrator (http://docs.systemviewinc.com) (AWS marketplace link: https://aws.amazon.com/marketplace/pp/B071Z6QDFP?qid=1496280052532).

Disclaimer: I'm one of the key contributor of the tool and the tool is based off Xilinx Vivado (authorized by Xilinx, of course.)

The pull request is specific to Visual System Integrator support for AWS F1 platform and contains CL Scripts that automate the workflow for bitstream generation. Thus this repo seems like the natural place to put those scripts.

The way you init variable in check_s3_bucket_policy.py is incorrect

in aws-fpga/hdk/common/scripts/check_s3_bucket_policy.py:

you init the variables like this:

class PolicyStatement:
    def __init__(self, statement, principal=None):
        self.statement = statement
        self.process_policy_statement(statement, principal)
        self.principals_re = []
        self.actions_re = []
        self.notactions_re = []
        self.resources_re = []

While, you use self.principals_re in the method process_policy_statement, it will cause an error like this:

AttributeError: PolicyStatement instance has no attribute 'principals_re'

The right sequence should be:

class PolicyStatement:
    def __init__(self, statement, principal=None):
        self.statement = statement
        self.principals_re = []
        self.actions_re = []
        self.notactions_re = []
        self.resources_re = []

        self.process_policy_statement(statement, principal)

Syntax error at 1385

I'm trying to execute this python script, but this error occured.

Traceback (most recent call last):
File "./check_s3_bucket_policy.py", line 1385, in
logger.debug("{0} inline policy: {1}".format(policy_name))
IndexError: tuple index out of range

I guess the first argument of format() was removed by mistake.
The correct code is as follows, right?

logger.debug("{0} inline policy: {1}".format(group_name, policy_name))

Unable to run helloworld_ocl on AMI 1.4.0

On the latest AMI1.4.0 I tried compiling the helloworld_ocl example and run it on hardware. After uploading it my S3 bucket and programming it back to the FPGA I get an error on the first attempt, where the host program tries to create a CL::Buffer.

Adding error handling to the CL::Buffer it's clear that I get error '-6', which is CL_OUT_OF_HOST_MEMORY.

I tried modifying the helloworld example to just allocate 1 byte, result is the same. Can someone reproduce this?

-- Yes, I know I should have used to AWS forum, but apparently: 'Your message quota has been reached. Please try again later.' I posted 1 reply today... sigh

Gitter link 404s

Steps to reproduce: Try going to https://gitter.im/aws/aws-fpga?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge by clicking the link in the github-displayed README.md.

create_sdaccel_afi.sh cannot connect to the S3 endpoint

kristopk may suggest to post this issue on AWS forum, but I could not find any discussion on 'create_sdaccel_afi.sh' on the forum.

I tried to make awsxclbin from xclbin using create_sdaccel_afi.sh,

[centos@AWS] $SDACCEL_DIR/tools/create_sdaccel_afi.sh -xclbin=krnl_vadd.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin -o=krnl_vadd.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin -s3_bucket=sdaccel-fpga -s3_dcp_key=sdaccel-dcp -s3_logs_ke=sdaccel-log

but error occurs.

...
INFO: Split DCP from xclbin: 18_08_26-072403-primary.bit
INFO: Split Metadata from xclbin: 18_08_26-072403-primary.bit
INFO: Generated manifest file '18_08_26-072403_manifest.txt'
upload failed: ./18_08_26-072403_Developer_SDAccel_Kernel.tar to s3://sdaccel-fpga/sdaccel-dcp/18_08_26-072403_Developer_SDAccel_Kernel.tar Could not connect to the endpoint URL: "https://sdaccel-fpga.s3.us-east-1c.amazonaws.com/sdaccel-dcp/18_08_26-072403_Developer_SDAccel_Kernel.tar?uploads"

I have S3 bucket and DCP and LOG sub-directory on S3.
Thanks.

Release version

Issue

Description

Steps to reproduce

You are not licensed to encrypt IEEE1735 Version 2

@aws/f1-fpga-hardware-development-kit

Release version
HDK_VERSION=1.2.0
AMI Version: 1.2.1

Expected Behavior
examples build as described

Actual Behavior
both cl_dram_dma and cl_hello_world fail with the above message on a new AMI image created today.

Steps to reproduce

[centos@ip-172-31-15-221 scripts]$  cd /home/centos/aws-fpga/hdk/cl/examples/
[centos@ip-172-31-15-221 cl_dram_dma]$ export CL_DIR=$(pwd)
[centos@ip-172-31-15-221 cl_dram_dma]$  cd $CL_DIR/build/scripts
[centos@ip-172-31-15-221 scripts]$ ./aws_build_dcp_from_cl.sh -notify

INFO: Starting the design checkpoint build process
INFO: Checking for proper environment variables and build directories
INFO: Environment variables and directories are present. Checking for Vivado installation.
INFO: Build through Vivado is running as background process, this may take few hours.
INFO: Output is being redirected to 17_05_15-183826.nohup.out
INFO: If you have set your EMAIL environment variable and -notify is specified, you will receive a notification when complete.
INFO:   (See $HDK_DIR/cl/examples/README.md for details)
[centos@ip-172-31-15-221 scripts]$ tail last_log
## file copy -force $UNUSED_TEMPLATES_DIR/unused_aurora_template.inc  $TARGET_DIR
## file copy -force $UNUSED_TEMPLATES_DIR/unused_hmc_template.inc     $TARGET_DIR
## file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
## exec chmod +w {*}[glob $TARGET_DIR/*]
## encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog  [glob -nocomplain -- $TARGET_DIR/*.?v] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
ERROR: [Vivado 12-3330] encrypt 1735: Failed to encrypt ''./home/centos/aws-fpga/hdk/cl/examples/cl_dram_dma/build/src_post_encryption/.temp/vivado_keyfile.txt: You are not licensed to encrypt IEEE1735 Version 2 [/home/centos/aws-fpga/hdk/cl/examples/cl_dram_dma/build/src_post_encryption/.temp/vivado_keyfile.txt]

    while executing
"source encrypt.tcl"
    (file "create_dcp_from_cl.tcl" line 167)

aws / aws-fpga Goto Github PK

aws-fpga's Introduction

Table of Contents

Overview of AWS EC2 FPGA Development Kit

Developer Support

Development Flow

Development Environments

FPGA Developer AMI

Xilinx tool support

End of life Announcements

Hardware Development Kit (HDK)

AWS Shells

Software-defined Development Environment

Runtime Tools (SDK)

Amazon EC2 F1 Platform Features

Getting Started

Getting familiar with AWS

Setting up development environment for the first time

Quickstarts

How Tos

Documentation Overview

aws-fpga's People

Stargazers

Watchers

Forkers

aws-fpga's Issues

Make AFI public:

Release version

Expected Behavior

Actual Behavior

Steps to reproduce

Release version

Feature request

Release version

Feature request

Release version

Expected Behavior

Actual Behavior

Steps to reproduce

Release version

Expected Behavior

Actual Behavior

Steps to reproduce

Release version

Expected Behavior

Actual Behavior

Steps to reproduce

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Issue

Description

Steps to reproduce

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