| Mnemonic | Nibble Encoding [caps = nibble, small = 2 bit] | Sample Instruction | Explanation | Comments |
|---|---|---|---|---|
| Arith. | ||||
| ADD | 000 XXXXx dD Ss tT | ADD R3, R2, R1 | R3 <= R2 + R1 | ALU arithmetic. Leverages ALU unit to perform basic add, subtract, and and xor instructions and some variations on the same. |
| ADDZ | 001 XXXXx dD Ss tT | ADDZ R6, R5, R4 | R6 <= R5 + R4 only if Z=1 | |
| SUB | 002 XXXXx dD Ss tT | SUB R9, R8, R7 | R9 <= R8 – R7 | |
| AND | 003 XXXXx dD Ss tT | AND R1, R2, R3 | R1 <= R2 & R3 | |
| NOR | 004 XXXXx dD Ss tT | NOR R1, R2, R3 | R1 <= ~ (R2 | R3) | |
| Shift | ||||
| SLL | 005 XXXXx dD Ss iI | SLL R1, R0, IMM | R1 <= R0 << IMM | |
| SRL | 006 XXXXx dD Ss iI | SRL R1, R0, IMM | R1 <= R0 >> IMM | |
| SRA | 007 XXXXx dD Ss iI | SRL R3, R2, IMM | R3 <= R2 >> IMM | |
| Load/ Store | ||||
| LW | 008 XXXXx dD Ss iI | LW R7, R6, 5 | R7 <= mem[R6+5] | load reg into mem |
| SW | 009 XXXXx dD Ss iI | SW R12, R14, 13 | Mem[R14 +13] <= R12 | store reg into mem |
| LHB | 00A XXXXx dD I I I | LHB R13, 12 | R13 <= {12, R13[7:0]} | load upper 8 bits into reg |
| LLB | 00B XXXXx dD I I I | LLB R12, 11 | R12 <= sign-extend {11} | load lower 8 bits into reg |
| Branch | ||||
| NEQ | 00C C XXXXXX iiii | B NEQ, LABEL | Branch if Z=0 | Branch target address = (Address of branch instruction + 1) + offset. PC holds word addresses, each instruction is 1 word, offset is specified as the number of instructions with respect to the instruction following the branch instruction. |
| EQ | 00C C XXXXXX iiii | B EQ, LABEL | Branch if Z=1 | |
| GT | 00C C XXXXXX iiii | B GT, LABEL | Branch if {Z,N}==2'b00 | |
| LT | 00C C XXXXXX iiii | B LT, LABEL | Branch if N=1 | |
| GTE | 00C C XXXXXX iiii | B GTE, LABEL | Branch if N=0 | |
| LTE | 00C C XXXXXX iiii | B LTE, LABEL | Branch if N=1 or Z=1 | |
| OVFL | 00C C XXXXXX iiii | B OVFL, LABEL | Branch if V=1 | |
| UNCOND | 00C C XXXXXX iiii | B UNCOND, LABEL | Branch unconditionally | |
| Jump | ||||
| JAL | 00D XXXXXx iIII | JAL LABEL | R15 <= (Address of JAL instruction + 1) Jump to target address | Jump target address = (Address of jal instruction + 1) + offset |
| JR | 00E XXXXXx iIII | JR R15 | Jump to target address given by contents of R15 | Return from function calls. |
| HLT | 00F XXXXXXXXX | HLT | Halt the processor | Halt processor execution. |
| Arith. | ||||
| NAND | 010 XXXXx dD Ss tT | NAND R3, R2, R1 | R3 <= ~ (R2 & R1) | Arithmetic instructions to complete the set of all 2 input gates, and their complement functions. |
| OR | 011 XXXXx dD Ss tT | OR R3, R2, R1 | R3 <= (R2 | R1) | |
| NOT | 012 XXXXx dD Ss xX | NOT R3, R2 | R3 <= ~ (R2) | |
| XOR | 013 XXXXx dD Ss tT | XOR R3, R2, R1 | R3 <= (R2 ^ R1) | |
| XNOR | 014 XXXXx dD Ss tT | XNOR R3, R2, R1 | R3 <= ~ (R2 ^ R1) | |
| UMULO | 015 XXXXx dD Ss tT | UMULO R3, R2, R1 | R3 <= R2 * R1 Unconstrained Overflow Unsigned Multiplication. | 16 bits by 16-bit multiplication of R1 and R2, discard the top 16 bits of the result in all cases to store the 16-bit result in R3. |
| UMULC | 016 XXXXx dD Ss tT | UMULC R3, R2, R1 | R3 <= unsigned {lowerbyte (R2) * lowerbyte(R1)} Constrained Unsigned Multiplication. | 1 byte by 1 byte multiplication in the unsigned context. Raises N, Z, V flags. |
| SMUL | 017 XXXXx dD Ss tT | SMUL R3, R2, R1 | R3 <= signed {lowerbyte (R2) * lowerbyte(R1)} Constrained Signed Multiplication. | 1 byte by 1 byte multiplication in the signed context. Raises N, Z, V flags. |
| Immd. | ||||
| ADDI | 018 XXXXx dD Ss iI | ADDI R2, R1, IMM | R2 <= R1 + IMM | ALU arithmetic but uses an immediate value (1, 2, 10, etc) instead of the contents of a reg. Immediate values are zero extended from lower 6 bits. Therefore, a value of 0 to 63 can be used as the immediate. |
| SUBI | 019 XXXXx dD Ss iI | SUBI R3, R2, IMM | R3 <= R2 - IMM | |
| ANDI | 01A XXXXx dD Ss iI | ANDI, R4, R3, IMM | R4 <= R3 & IMM | |
| NANDI | 01B XXXXx dD Ss iI | NANDI R5, R4, IMM | R5 <= ~ (R4 & IMM) | |
| ORI | 01C XXXXx dD Ss iI | ORI R6, R5, IMM | R6 <= R5 | IMM | |
| NORI | 01D XXXXx dD Ss iI | NORI R7, R6, IMM | R7 <= ~ (R6 | IMM) | |
| XORI | 01E XXXXx dD Ss iI | XOR R8, R7, IMM | R8 <= R7 ^ IMM | |
| XNORI | 01F XXXXx dD Ss iI | XORNI R9, R8, IMM | R9 <= ~ (R8 ^ IMM) | |
| UMULI | 020 XXXXx dD Ss iI | UMULI R10, R9, IMM | R10 <= unsigned {lowerbyte (R9) * zero_extend_to_8_bits (IMM)} | |
| SMULI | 021 XXXXx dD Ss iI | SMULI R11, R10, IMM | R11 <= unsigned {lowerbyte (R10) * zero_extend_to_8_bits (IMM)} | |
| Double Immediates | ||||
| ADDII | 022 XXXXx dD Ii jJ | ADDII R1, IMM_I, IMM_J | R1 <= IMM_I + IMM_J | Each immediate is zero extended from 6 bits. Raises N, Z, V flags. |
| SUBII | 023 XXXXx dD Ii jJ | SUBII R2, IMM_I, IMM_J | R2 <= IMM_I – IMM_J | Each immediate is zero extended from 6 bits. Raises N, Z, V flags. |
| MULII | 024 XXXXx dD Ii jJ | MULII R3, IMM_I, IMM_J | R3 <= IMM_I * IMM_J | Each immediate is zero extended from 6 bits. Raises N, Z, V flags. |
| Complex Arith. | ||||
| DIV | 025 XXXXx dD Ss tT | DIV R3, R2, R1 | R3 <= unsigned {R2 / R1} | Result is rounded down to nearest whole number. Raises Z flags. |
| SDIV | 026 XXXXx dD Ss tT | DIV R6, R5, R4 | R6 <= signed {R5 / R4} | Result is rounded down to nearest whole number. Signs are heeded for both reg values. Raises Z flags. |
| DIVI | 027 XXXXx dD Ss iI | DIV R8, R7, IMM | R8 <= unsigned {R7 / IMM} | Result is rounded down to nearest whole number. Each immediate is zero extended from 6 bits. Raises Z flags. |
| Other notes: | Flag registers are Z-zero, V-overflow (positive and negative), N-negative/sign R0 is a zero register R15 is the return address for JAL. Should not write to this register R13, R14 is our stack and base pointer |
ayandeephazra / cisc-v Goto Github PK
View Code? Open in Web Editor NEWGithub Repo that seeks to build a SIMD CISC processor.
License: MIT License
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