SFENCE requires sec_opcd about x86reference HOT 4 CLOSED

The Intel manual explicitly says:

Specification of the instruction's opcode above indicates a ModR/M byte of F8. For this instruction, the processor
ignores the r/m field of the ModR/M byte. Thus, SFENCE is encoded by any opcode of the form 0F AE Fx, where x
is in the range 8-F

from x86reference.

Yea you're correct I missed it in felix's docs.
Although I'm not sure he grabbed this from the Intel manual, as far as I can tell this is all the given information about SFENCE in the manual:

The SFENCE (Store Fence) instruction controls write ordering by creating a fence for memory store operations. This
instruction guarantees that the result of every store instruction that precedes the store fence in program order is
globally visible before any store instruction that follows the fence. The SFENCE instruction provides an efficient way
of ensuring ordering between procedures that produce weakly-ordered data and procedures that consume that
data.

Page 252 section 10.4.6.4.

Also disassemblers like objdump and capstone doesn't recognize this instruction if not used with F8 ModR/M byte.
You can confirm objdump disassembly here,
and capstone disassembly here.

You have any idea maybe where this quote is from since I couldn't find it in the manual and the other disassemblers disagree.

from x86reference.

This is the right one, page 601:

https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2b-manual.html

from x86reference.

This is the right one, page 601:

https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2b-manual.html

Hmmm interesting.
Wonder why other disassemblers missed it.
Guessed this can be closed :)

from x86reference.