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This is Processor Accelerator Architecture Simulator (PAAS) for heterogeneous computing system.

PAAS integrates gem5 and Verilator and further develops the infrastructure of the two simulators to provide system designers 
with unique features for system simulation and exploration:

    a) Co-simulation of hardware accelerators (described in Verilog), CPUs and memory system
    b) Shared virtual address space between accelerators and CPUs
    c) Runtime control of accelerators
    d) Capabilities of accelerators for exploiting both fine-grained and coarse-grained memory access
    e) Support of flexible architecture (eg. accelerator coherency port)
    f) Parallized simulation and reconfigurability of FPGA-based accelerator

If you have questions or ask for a manual, please send mail to [email protected]

Enjoy using PAAS and please share your modifications and extensions.

Compared to gem5, there are things of original gem5 have been modified, so please note them:

'AllMemory'     in     params.py 
'translate'     in     tlb.cc
fpga part       in     the directories: ./src/mem, ./src/arch, ./src/cpu

Some examples of designs can be found in ./configs and hope them will help you undenstand the basic description of archtecture.