Pipeline must contain at least 5 sages:

• fetch
• decode
• execute
• memory
• writeback

Must ensure that the pipeline correctly handles instruction dependencies, and also blocks/stalls

Does not need to implement forwarding or interrupt handling

Basically, I want the demo to confirm that you have a fully working cache and memory. This demo is more about ensuring that you have everything operating correctly, so you can build on top of that, and catching any mistakes before you go further. If there is something really wrong, I'll want you to fix it and show me again, so we can be sure you have it right. Monday is a chance to get everyone in the class checking everyone else's simulation, so every team can have a working memory subsystem. It's going to be important to watch what the other teams do and ask questions if you think they have missed anything - I may not catch some detail that you will, which might save them a lot of headaches down the line.

Your view command should return the tag, contents, dirty, and valid bit values for a given cache line, and should just return the contents of a block in DRAM if you tell it to view that level. Think of it as your debugging probe for the simulation.

Your demo should show the cache and memory empty at some locations, then you write some things, then show they are in the proper places (depends on your write policy), then read some, and show that they are in the right places. You should also show that two conflicting accesses cause an eviction, and that it handles dirty versus clean evictions.

Remember that if you use an allocate policy for writing, the cache loads the entire line first, then overwrites the specific word. The memory only needs to delay two or three cycles for the demo, so you don't have to issue as many commands. Your driver program should keep a count of the commands issued as a first cut at the cycle counter for the simulator.

Program must demonstrate all of the basic operations

• load/store
• register to register arithmetic
• conditional branch

A good demonstration is the equivalent of a for loop that reads a series of pairs of values from memory, adds them, stores the results back to memory, and exits when (read: if, ie. conditional branch) the loop control counter reaches the termination condition.

implement opcodes to demonstrate all basic functionality

• load
• store
• At least 1 ALU op
  • add
  • subtract
  • multiply
  • divide
  • logical shifts
• conditional branch

Optional:

• Single special operation
  • For us, do the key generation operation
• Unconditional op
  opcodes must be encoded in binary as integers

Must be able to:

• view contents of each pipeline stage
• controlled execution of the pipeline:
  • single step
  • execute until breakpoint
  • run for a specified number of cycles
• load programs
• save programs/state
• reset state

Implement debugging interface that can selectively view portions of memory.

Implement debugging interface to allow users to read/write, and display the contents of the cache or ram