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@BrendenPage, @taylor-bsg,
this is the PR that contains the gold.v (BSG original netlist) and dut.v (Surelog/Yosys) pairs. One pair per directory.
chipsalliance/synlig#1601

Please run some verification on each pair and report eventual errors.
Thanks

@BrendenPage, @taylor-bsg ,

grep -r bsg_expand_bitmask ./bsg_micro_designs/bsg_cache/bsg_cache_dma/src/
./bsg_micro_designs/bsg_cache/bsg_cache_dma/src/bsg_cache_dma.v: bsg_expand_bitmask #(
./bsg_micro_designs/bsg_cache/bsg_cache_dma/src/bsg_cache_dma.v: bsg_expand_bitmask #(
./bsg_micro_designs/bsg_cache/bsg_cache_dma/src/bsg_cache.v: bsg_expand_bitmask #(
./bsg_micro_designs/bsg_cache/bsg_cache_dma/src/bsg_cache.v: bsg_expand_bitmask #(
./bsg_micro_designs/bsg_cache/bsg_cache_dma/src/bsg_cache.v: bsg_expand_bitmask #(

There is no definition for this module "bsg_expand_bitmask" in the test.

Test: bsg_micro_designs/bsg_dataflow/bsg_sbox/bsg_sbox_num_channels_p_16_channel_width_p_32/top.v

contains a blackbox \bsg_scatter_gather_vec_size_lp16 which render formal verification impossible

4.1.1. Analyzing design hierarchy..
Top module: \top
Used module: \bsg_sbox
Used module: \FDRE
Used module: \INV
Used module: \LUT2
Used module: \LUT6
Used module: \MUXF8
Used module: \MUXF7
Used module: \LUT4
Used module: \LUT3
Used module: \LUT1
Used module: \LUT5
Used module: \IBUF
Used module: \OBUF
Used module: \BUFG
ERROR: Module \bsg_scatter_gather_vec_size_lp16' referenced in module \bsg_sbox' in cell `\bsg' is not part of the design.