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followers: 142.0 following: 39.0 repos: 182.0 gists: 20.0

Name: Alex Bucknall

Type: User

Company: @arribada

Bio: Conservation Technologist. Electronic Engineer. Edge Computing, FPGA SoCs, MCUs.

Twitter: AlexRBucknall

Location: Hove, UK

Blog: bucknalla.dev

Hi, I'm Alex 👋

I'm a Software/Hardware Engineer living in Brighton, United Kingdom.

I recently finished a PhD in Reconfigurable Computing at Warwick University's WARC group

Previously I was a Software Engineer at balena, working on tools for IoT fleet management and designing Hardware-in-Loop testing tooling.

Currently I'm a Senior Embedded Software Engineering at Arribada, developing open, customisable and impact-driven technologies for conservation organisations, working to support the goals of wildlife conservation.

🌱 I’m currently learning Zephyr, Amaranth(HDL), and Typescript
👯 I’m looking to collaborate on open source tooling and frameworks for FPGAs & SoCs
💬 Ask me about partial reconfiguration, electronics, and programmable logic
📫 How to reach me: Twitter
😄 Pronouns: he/him
⚡ Fun fact: I own a Moto Guzzi V7 MKI and talk way too much about it

Alex Bucknall's Projects

silabs_blue_gecko_cmake_example

Example project for Silabs BGM111/BGM113 Blue Gecko module using CMake and GCC

slackin

Public Slack organizations made easy

smartpi

$4 Smarthome with ESP8266 and Firebase. Works with IFTTT, HomeKit (Siri), has a web app

starhaven-blog

steamlink

RPi 3B+ SteamLink

tailscale-block

theme-faq

Theme for publishing a FAQ or Knowledge base

todo-to-issue-action

Action that converts TODO comments to GitHub issues on push.

trumptalks

WarwickHACK17 - Trump Talks Project

ts100

Open Source firmware for the ts100 iron

uart_de0_nano

UART serial interface on DE0-Nano

udmabuf

User space mappable dma buffer device driver for Linux.

ultra96-csi-mezzanine

Mezzanine for Ultra96 CSI Camera

ultra96-dna

Get UUID from DNA Registers on Ultra96

ultra96-gpio-mezzanine

96Board compliant mezzanine for the Ultra96 ZynqMP board

ultra96fancontrol

Fan Control IP

unofficial-hltv-api

My custom 'API' for hltv.org, allows the module to be imported and used with parameters to get data from certain aspects of the site.

utils

a set of simple utilities in c for microcontrollers

vcd_parser

A VCD parser object

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-snippets

Verilog Snippets for VSCode

vivado-ci

A simple Vivado (Verilog & VHDL) Continuous Integration tool with seamless integration to Travis-CI

vj-uart

Virtual JTAG UART for Altera Devices

wake-on-lan

Wake over LAN balenablock

warc_fusesoc

WARC Open Fusesoc Cores Repository

wavedrom

:ocean: Digital timing diagram in your browser

xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

bucknalla Goto Github PK

Hi, I'm Alex 👋

Alex Bucknall's Projects

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