chengzhangxinli / altera-pcie Goto Github PK

This is a minimal Altera PCI-Express project, including Linux driver & userspace examples, the requisite Altera PCIe core and supporting logic for implementing a range of 32-bit read/write registers in the FPGA, and a pair of circular buffers allowing the CPU to send and receive messages. The Linux driver is licensed under the GPLv3, and everything else is under the MIT license. Notice that this repository has a few git submodules, so when you clone this repo, be sure to use the --recursive option. The reason for splitting out into separate repos is to allow you to easily incorporate the logic into your own projects.

Before you begin, you'll need to set PROJ_HOME to the location where you cloned this repo, and ALTERA to your Quartus installation:

$ cd $HOME
$ git clone --recursive [email protected]:makestuff/altera-pcie.git
Cloning into 'altera-pcie'...
  :
$ cd altera-pcie
$ export PROJ_HOME=$(pwd)
$ export ALTERA=/usr/local/altera-16.1  # or wherever
$ ls $ALTERA
hld  hls  ip  licenses	logs  modelsim_ae  nios2eds  quartus  uninstall
$

The submodules are:

• hdl-tools: This contains the files needed to build and test any project.
• pcie-driver: This is the Linux device-driver (based on altpciechdma.c) and a C++ userspace API.
• ip/makestuff/altera-libs: Altera simulation libraries for low-level FPGA resources.
• ip/makestuff/buffer-fifo: A generic single-clock FIFO.
• ip/makestuff/block-ram: A collection of block-RAM modules.
• ip/makestuff/dvr-rng: A synthesizable random-number-generator, for testing purposes.
• ip/makestuff/pcie-hip: The PCIe hard-IP and supporting logic.

Finally, we have two example applications, each containing:

• A top-level design capable of being built into an FPGA, either Cyclone V or Stratix V.
• A C++ example which connects to the FPGA via the driver.
• A system-simulation testbench.

We have:

• apps/demo: This demonstrates the FPGA registers and the two circular-buffers.
• apps/bench: This provides some crude tools for measuring round-trip latency.