Comments (3)
env
should be "installed" as part of pulling a git submodule. Please enter the 5 commands from the Rocket Chip README. It seems like you might have forgotten the last one.
from rocket-chip.
Thanks for your quick help.
I think this step was very long
git submodule update --init
and I forgot to do this step
git submodule update --init --recursive riscv-tests
After I ran the above step and then
make -j8 run-asm-tests
how do I know if the test ran properly (so that I can have confidence in the installation flow)?
I can view the output/*.out but there is no indication of PASS/FAIL.
from rocket-chip.
No indication is a sign of success (or more precisely, the return code of the execution command given to the Makefile marks a success). Failures and assertions are printed to the *.out files, and return error codes to the Makefile, and in turn to the command line.
from rocket-chip.
Related Issues (20)
- firtool: Unknown command line argument '-disable-infer-rw'. Try: 'firtool --help' HOT 7
- Any store-related instruction between LoadReserved and StoreConditional combination will break the reservation HOT 3
- sc.w was executed incorrectly in Rocket HOT 1
- Running a custom binary after changing the rocket-chip configuration HOT 1
- RationalCrossing broken in fast to slow clock direction HOT 1
- HLV/HSV flushes pipeline HOT 1
- How to generate rocket chip in verilog HOT 4
- How to generate Boom core on other FPGA platforms like zcu102 HOT 3
- Remove Scalar Crypto HOT 4
- Embrace new world Chisel. HOT 12
- SimJTAG connecting to OpenOCD HOT 1
- How to Remove PTW from Rocket Core. HOT 2
- LR/SC unexpectedly fails when there is a jump in program HOT 1
- It is needed to clarify dependent tools version HOT 5
- Error in AXI4 Xbar with unused fields HOT 1
- Executing c.fld on Rocket chip load the wrong value in the destination register HOT 1
- Divide by zero on the Rocket chip and writes `0x0` to `rd` instead of `0xffffffffffffffff`
- REMU `x` by zero on the Rocket chip writes `0x0` to `rd` instead of `x` HOT 1
- "Hello world" simulation target and instruction in README.md
- can I remove the itim and tlb from the icache ? HOT 1
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