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module Test where

import CLasH.HardwareTypes
import Prelude hiding (Maybe(..),($),(.))
data Maybe a = Just a | Nothing
    deriving Show

infixr 0 $
($) a = a

infixr 9 .
(.) a b c = a (b c)

test0 :: Bit -> Bit
test0 Low = High
test0 High = Low

{-# ANN test1 TopEntity #-}
test1 :: Bit -> Bit
test1 = test0 . test0

architecture structural of test1Component_0 is
begin
     comp_ins_res2046865544 : entity .Component_1
                                   port map (param2046865564 => param2046865542,
                                             res2046865566 => res2046865544,
                                             resetn => resetn);
end architecture structural;

module Test where
import CLasH.HardwareTypes
{-# ANN test TopEntity #-}
test :: Vector D32 Bit -> Vector D16 Bit
test a = fst (vsplit a)

 splitPrimNamez20UZLNSimplez20Uz22Ua2046865519z22UZR : block
 begin
      arg2046865524.A <= arg2046865524(0 to 15);
      arg2046865524.B <= arg2046865524(16 to 31);
 end block splitPrimNamez20UZLNSimplez20Uz22Ua2046865519z22UZR;

 type Z2TZLz2cUZRvectorzmstd_logiczm0_to_15vectorzmstd_logiczm0_to_15 is
      record A : vectorzmstd_logiczm0_to_15;
             B : vectorzmstd_logiczm0_to_15;
      end record;

testComponent_0.vhdl:27:43: type of prefix is not an array
testComponent_0.vhdl:28:43: type of prefix is not an array