Hey all:
I installed the SDx 2017.2 tool in Ubuntu and was able to generate CSIM and almost finished the FPGA build.

However, I got this error when run 'make' under sdsoc_build and I didn't see the bitstream and uImage were generated.

Appreciate any suggestions.

Finished 1st of 5 tasks (FPGA synthesis). Elapsed time: 00h 31m 01s.
.....
Finished 2nd of 5 tasks (FPGA logic optimization). Elapsed time: 00h 00m 40s.
.....................
Finished 3rd of 5 tasks (FPGA logic placement). Elapsed time: 00h 03m 18s.
.........................
Finished 4th of 5 tasks (FPGA routing). Elapsed time: 00h 04m 35s.

===>The following messages were generated while  Compiling (bitstream) opencl binary: bin Log file: /home/ubuntu/workspace/bnn_fpga/cpp/accel/sdsoc_build/_sds/p0/_vpl/ipi/ipiimpl/ipiimpl.runs/impl_1/runme.log  :
ERROR: [VPL-1] Design failed to meet timing
WARNING: [VPL 60-732] Link warning: There is no resource utilization data in DSA, utilization DRC is skipped
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, route_design ERROR
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx/SDx/2017.2/bin/vpl  --iprepo /home/ubuntu/workspace/bnn_fpga/cpp/accel/sdsoc_build/_sds/iprepo/repo  --iprepo /opt/Xilinx/SDx/2017.2/data/ip/xilinx  --platform /opt/Xilinx/SDx/2017.2/platforms/zed/zed.xpfm  --temp_dir /home/ubuntu/workspace/bnn_fpga/cpp/accel/sdsoc_build/_sds/p0  --output_dir /home/ubuntu/workspace/bnn_fpga/cpp/accel/sdsoc_build/_sds/p0/vpl  --input_file /home/ubuntu/workspace/bnn_fpga/cpp/accel/sdsoc_build/_sds/p0/.xsd/top.bd.tcl  --target hw   --save_temps  --kernels top --webtalk_flag SDSoC'
sds++ log file saved as /home/ubuntu/workspace/bnn_fpga/cpp/accel/sdsoc_build/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

Makefile:35: recipe for target 'accel_test_bnn.exe' failed
make: *** [accel_test_bnn.exe] Error 1

The ParamsIO.cpp and ZipIO.cpp load *.zip file as parameters. If I want to use my own training parameters, for example, generated by numpy.savez(_compressed) as *.npz,
how do I get *.zip from *.npz?

Dear author,

I am trying to use your weight (params) to directly inference your data by using tensorflow. However, I cannot get the same output result from your hardware. I have reshaped the input image into (batch, C, H,W ) and the weight into (K,C,H,W). But your hardware output (fixed_buffer result before batch norm) is different from my software output. Do you have any idea why is that happening? (I have also considered the zero padding issue).

@rzhao01
Hi, sorry to bother you again.

Any chance that the code can be shifted to CNN version??
Like I put some trained CNN weight and predict the accuracy? Running on ARM.

Or maybe I just need to modify the code related to prediction? And which part is used for prediction? I am confused.

when mak in cpp，I have a problem ‘’max_align_t‘’.
In file included from /opt/Xilinx/SDx/2016.4/Vivado_HLS/include/gmp.h:53:0,
from /opt/Xilinx/SDx/2016.4/Vivado_HLS/include/floating_point_v7_0_bitacc_cmodel.h:143,
from /opt/Xilinx/SDx/2016.4/Vivado_HLS/include/hls_half.h:40,
from /opt/Xilinx/SDx/2016.4/Vivado_HLS/include/ap_int.h:28,
from ../utils/Typedefs.h:4,
from AccelTest.h:4,
from AccelTest.cpp:1:
/usr/include/c++/5/cstddef:51:11: error: ‘::max_align_t’ has not been declared
using ::max_align_t;
^

I add #include to
ParamIO.cpp
Common.cpp
DataIO.cpp
AccelTest.cpp
can solve this problem.

But, this wether lead other problem, since
'ParamIO.cpp
Common.cpp
DataIO.cpp
AccelTest.cpp'
will be build by Vivado_HLS?

As you can see, the code only predicts label 7, and we don't quite sure where the problem is.

We use the parameters extracted from Pytorch. And we also changed the input value range [-1,1] as the Theano version did.

Hello, when I make the Makefile in the ' cpp/accel/sdsoc_build ' , errors about the SDSoC license occurs.

I have get the corrected license and it show 'yes' in the Xilinx license manage.
(by the ways, I am using the SDx and set the $PATH to the SDX/bin)
Any advices will be appreciated.

Hi！ When I run make -j4 command for the sdsoc_build makefile, I have a issue. I used Ubuntu 16.04 OS, 2017.1 SDSoc software.

when I run xdlmcheck ap_sdsoc command, it shows the same problem with my SDSOC

Thank you!

Hi, I am trying to understand, how is the Padding done in your code? Are you taking each channel and you performing the padding? as an e.g. a (32*32) 1024 floating number that represents the red channel? or you perform the padding on the whole 3072 floating numbers?

Howdy y'all,

I have been trying to port this over to the UltraScale. It seems to be going alright, but when I run the application on the board, I predict mostly class 1 and class 2. I have made no changes to the code, other than compiling libraries in aarch64 to be compatible with the UltraScale.

I imagine there is some size_T typing I'm overlooking, but I can't seem to pick it out. Has anyone encountered this?

Hi Ritchie,

I find some errors while compiling the Makefile in "bnn/cpp/accel/sdsoc_build" on the Ubuntu 16.04 system. Here is the log information:

sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../accel_test_bnn.cpp -o accel_test_bnn.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g
sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../Accel.cpp -o Accel.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g
sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../AccelSchedule.cpp -o AccelSchedule.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g
sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../AccelTest.cpp -o AccelTest.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g
INFO: [SDSoC 0-0] Processing -sds-hw block for top
INFO: [SDSoC 0-0] Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
INFO: [SDSoC 0-0] Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
INFO: [SDSoC 0-0] Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
INFO: [SDSoC 0-0] Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux
INFO: [SDSoC 0-0] Using system configuration -sds-sys-config linux
INFO: [SDSoC 0-0] Using system configuration -sds-sys-config linux
INFO: [SDSoC 0-0] Using system configuration -sds-sys-config linux
INFO: [SDSoC 0-0] Using system configuration -sds-sys-config linux
child process exited abnormally
while executing
"exec which [apc_get_global APCC_TOOLCHAIN]-g++"
(procedure "sdscc_set_toolchain_config" line 27)
invoked from within
"sdscc_set_toolchain_config $toolchain_config $toolchain_type $proc_type $toolchain_name"
(file "/home/yu/Documents/SDSoc/SDx/2016.4/bin/xdcc.tcl" line 3616)
child process exited abnormally
while executing
"exec which [apc_get_global APCC_TOOLCHAIN]-g++"
(procedure "sdscc_set_toolchain_config" line 27)
invoked from within
"sdscc_set_toolchain_config $toolchain_config $toolchain_type $proc_type $toolchain_name"
(file "/home/yu/Documents/SDSoc/SDx/2016.4/bin/xdcc.tcl" line 3616)
Makefile:21: recipe for target 'Accel.o' failed
make: *** [Accel.o] Error 1
make: *** Waiting for unfinished jobs....
Makefile:21: recipe for target 'AccelTest.o' failed
make: *** [AccelTest.o] Error 1
child process exited abnormally
while executing
"exec which [apc_get_global APCC_TOOLCHAIN]-g++"
(procedure "sdscc_set_toolchain_config" line 27)
invoked from within
"sdscc_set_toolchain_config $toolchain_config $toolchain_type $proc_type $toolchain_name"
(file "/home/yu/Documents/SDSoc/SDx/2016.4/bin/xdcc.tcl" line 3616)
Makefile:21: recipe for target 'AccelSchedule.o' failed
make: *** [AccelSchedule.o] Error 1
child process exited abnormally
while executing
"exec which [apc_get_global APCC_TOOLCHAIN]-g++"
(procedure "sdscc_set_toolchain_config" line 27)
invoked from within
"sdscc_set_toolchain_config $toolchain_config $toolchain_type $proc_type $toolchain_name"
(file "/home/yu/Documents/SDSoc/SDx/2016.4/bin/xdcc.tcl" line 3616)
Makefile:27: recipe for target 'accel_test_bnn.o' failed
make: *** [accel_test_bnn.o] Error 1

Could you please help me fix these compiler errors?

Thanks a lot for all your help.

i read the file in the params folder ,i am not understand why it is the 27 files? The first arr_0, i think it is the first conv layer weight params and the arr_3 is the sencond conv layer weight params ,but the arr_1,arr_2 what does it correspond ? Can you answer my confusion ? Otherwise, how can i get the 27 files in the neural networks ?

I'm trying to build your codes with SDSoC 2016.1 (also 2016.3)
but, I failed to build it when I followed the instructions in README.
I think it's because I set wrong C_INCLUDE_PATH before make.
Could you list the C_INCLUDE_PATH (or CPATH) you've used?

Thank you

When I run make -j4 on the fpga bitstream I keep getting this build error. Anyone ever run into this?

My setup follows the recommendation with Ubuntu 16.04 and SDSoC 2016.4

I tried to compile by specifying platform to microzed. But several errors came out like:

This design requires 28666 of such cell types but only 17600 compatible sites are available in the target device.

This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 154 of such cell types but only 120 compatible sites are available in the target device.

How can I modify this project to work on microzed. Could you give any instructions? Thanks!

I couldn't understand these codes, Accel.cpp#L624. And h01 Accel.cpp#L10 seems not being used. Could you please give a hint? Thanks so much!

Hi, Ritchie @rzhao01

I am working on the cifar-10 classification project based on Pytorch. And I got a question that do I have to change the data in these two files due to the shift of platform?

Second, I am wandering if you can tell me how do you create these two files? I want to create my own test input files but I don't know how.

Thank you so much.

when I make sdsoc_build to generate FPGA bitstream.
One error has happened:

INFO: [SDSoC 0-0] Performing accelerator source linting for top
INFO: [SDSoC 0-0] Moving function top to Programmable Logic
ERROR: [HLS 200-70] Compilation errors found:
Pragma processor failed: In file included from /home/songqingzeng/bnn-fpga-master/cpp/accel/Accel.cpp:1:
In file included from /opt/Xilinx/SDx/2016.4/Vivado_HLS/lnx64/tools/gcc/lib/gcc/x86_64-unknown-linux-gnu/4.6.3/../../../../include/c++/4.6.3/cstddef:42:
In file included from /opt/Xilinx/SDx/2016.4/Vivado_HLS/lnx64/tools/gcc/lib/gcc/x86_64-unknown-linux-gnu/4.6.3/../../../../include/c++/4.6.3/x86_64-unknown-linux-gnu/32/bits/c++config.h:393:
In file included from /opt/Xilinx/SDx/2016.4/Vivado_HLS/lnx64/tools/gcc/lib/gcc/x86_64-unknown-linux-gnu/4.6.3/../../../../include/c++/4.6.3/x86_64-unknown-linux-gnu/32/bits/os_defines.h:40:
/usr/include/features.h:367:12: fatal error: 'sys/cdefs.h' file not found

include <sys/cdefs.h>

       ^

ERROR: [SDSoC 0-0] Exiting sds++ : Error when calling '/opt/Xilinx/SDx/2016.4/Vivado_HLS/bin/vivado_hls /home/songqingzeng/bnn-fpga-master/cpp/accel/sdsoc_build/_sds/vhls/top_run.tcl'
sds++ log file saved as /home/songqingzeng/bnn-fpga-master/cpp/accel/sdsoc_build/_sds/reports/sds_Accel.log
ERROR: [SDSoC 0-0] Build failed

Makefile:21: recipe for target 'Accel.o' failed
make: *** [Accel.o] Error 1

I don`t known the reason of this.

I think the file (/usr/include/features.h) shound not been bulid by sds++.
May be the evn PATH is error.
Thank all.

Hi all, after I build the FPGA bitstream with the default project, I always got Timing constraints are not met. Is there any possible solution to this issue?

I have this problem when I run the make -j4 in the sd_soc_build folder.
The concrete error is like:

Is there someone who encountered this?
My system is Ubuntu 14.04, and the SDSoC is 2017.2

hi, my SDSoC version is 2016.4 on Ubuntu 16.04, and i just follow the instruction in README. At first, the log shows something wrong with zlib.h. I downloaded the source and it seems to be resolved. But i still cannot compile the code.
the log message is:

make -C minizip
make[1]: Entering directory '/home/ml/bnn-fpga-master/cpp/minizip'
cc -c -O -I../.. -DHAVE_AES miniunz.c
cc -c -O -I../.. -DHAVE_AES unzip.c
cc -c -O -I../.. -DHAVE_AES ioapi.c
cc -c -O -I../.. -DHAVE_AES minizip.c
unzip.c: In function ‘unz64local_GetCurrentFileInfoInternal’:
unzip.c:898:17: warning: passing argument 3 of ‘unz64local_getByte’ from incompatible pointer type [enabled by default]
if (unz64local_getByte(&s->z_filefunc, s->filestream_with_CD, &uL) != UNZ_OK)
^
unzip.c:198:11: note: expected ‘int *’ but argument is of type ‘uLong ’
local int unz64local_getByte(const zlib_filefunc64_32_def pzlib_filefunc_def, voidpf filestream, int *pi)
^
unzip.c:902:17: warning: passing argument 3 of ‘unz64local_getByte’ from incompatible pointer type [enabled by default]
if (unz64local_getByte(&s->z_filefunc, s->filestream_with_CD, &uL) != UNZ_OK)
^
unzip.c:198:11: note: expected ‘int *’ but argument is of type ‘uLong ’
local int unz64local_getByte(const zlib_filefunc64_32_def pzlib_filefunc_def, voidpf filestream, int *pi)
^
unzip.c:907:17: warning: passing argument 3 of ‘unz64local_getByte’ from incompatible pointer type [enabled by default]
if (unz64local_getByte(&s->z_filefunc, s->filestream_with_CD, &uL) != UNZ_OK)
^
unzip.c:198:11: note: expected ‘int *’ but argument is of type ‘uLong ’
local int unz64local_getByte(const zlib_filefunc64_32_def pzlib_filefunc_def, voidpf filestream, int *pi)
^
cc -c -O -I../.. -DHAVE_AES zip.c
cc -O -I../.. -DHAVE_AES -o miniunz miniunz.o unzip.o ioapi.o libaes.a -lz
cc -O -I../.. -DHAVE_AES -o minizip minizip.o zip.o ioapi.o libaes.a -lz
ar rv ./libminizip.a miniunz.o unzip.o minizip.o zip.o ioapi.o
r - miniunz.o
r - unzip.o
r - minizip.o
r - zip.o
r - ioapi.o
ar rv ./libminizip.a miniunz.o unzip.o minizip.o zip.o ioapi.o
r - miniunz.o
r - unzip.o
r - minizip.o
r - zip.o
r - ioapi.o
ranlib ./libminizip.a
make[1]: Leaving directory '/home/ml/bnn-fpga-master/cpp/minizip'
make -C utils
make[1]: Entering directory '/home/ml/bnn-fpga-master/cpp/utils'
g++ -c DataIO.cpp -o DataIO.o -O3 -std=gnu++11 -g
g++ -c ParamIO.cpp -o ParamIO.o -O3 -std=gnu++11 -g
g++ -c ZipIO.cpp -o ZipIO.o -O3 -std=gnu++11 -g
g++ -c Timer.cpp -o Timer.o -O3 -std=gnu++11 -g
cc1plus: error: unrecognized command line option ‘-std=gnu++11’cc1plus: error: unrecognized command line option ‘-std=gnu++11’

cc1plus: error: unrecognized command line option ‘-std=gnu++11’
cc1plus: error: unrecognized command line option ‘-std=gnu++11’
Makefile:14: recipe for target 'DataIO.o' failed
make[1]: *** [DataIO.o] Error 1
make[1]: *** Waiting for unfinished jobs....
Makefile:14: recipe for target 'ZipIO.o' failed
make[1]: *** [ZipIO.o] Error 1
Makefile:14: recipe for target 'ParamIO.o' failed
make[1]: *** [ParamIO.o] Error 1
Makefile:14: recipe for target 'Timer.o' failed
make[1]: *** [Timer.o] Error 1
make[1]: Leaving directory '/home/ml/bnn-fpga-master/cpp/utils'
Makefile:3: recipe for target 'all' failed
make: *** [all] Error 2

is it something wrong with the version of c++? #3
thanks!

There were some errors when I compile the Makefile in bnn/cpp.
Here is the log

#:~/work/accel/bnn-fpga-master/cpp$ make -j4
make -C minizip
make[1]: Entering directory '/home/null/work/accel/bnn-fpga-master/cpp/minizip'
cc -O -I../.. -DHAVE_AES -o miniunz miniunz.o unzip.o ioapi.o libaes.a -lz
cc -O -I../.. -DHAVE_AES -o minizip minizip.o zip.o ioapi.o libaes.a -lz
/usr/bin/ld: libaes.a(aescrypt.o): relocation R_X86_64_32 against symbol t_fn' can not be used when making a PIE object; recompile with -fPIC /usr/bin/ld: libaes.a(aeskey.o): relocation R_X86_64_32 against symbol t_fl' can not be used when making a PIE object; recompile with -fPIC
/usr/bin/ld: final link failed: Nonrepresentable section on output
collect2: error: ld returned 1 exit status
Makefile:23: recipe for target 'miniunz' failed
make[1]: *** [miniunz] Error 1
make[1]: *** Waiting for unfinished jobs....
/usr/bin/ld: libaes.a(entropy.o): relocation R_X86_64_32 against .rodata.str1.1' can not be used when making a PIE object; recompile with -fPIC /usr/bin/ld: libaes.a(aescrypt.o): relocation R_X86_64_32 against symbol t_fn' can not be used when making a PIE object; recompile with -fPIC
/usr/bin/ld: libaes.a(aeskey.o): relocation R_X86_64_32 against symbol `t_fl' can not be used when making a PIE object; recompile with -fPIC
/usr/bin/ld: final link failed: Nonrepresentable section on output
collect2: error: ld returned 1 exit status
Makefile:26: recipe for target 'minizip' failed
make[1]: *** [minizip] Error 1
make[1]: Leaving directory '/home/null/work/accel/bnn-fpga-master/cpp/minizip'
Makefile:5: recipe for target 'all' failed
make: *** [all] Error 2

When I run the project with accel_test_bnn.cpp, I meet with the following error: how to deal with it? I run the project on Win7 Platform and use HLS 2017.1.
.../bnn-fpga-master/bnn-fpga-master/cpp/accel/../minizip/zip.h:23:20: fatal error: zlib.h: No such file or directory compilation terminated.

Hi , my SDSOC version is 2017.2 on ubuntu 16.04 with g++4.8

While executing "make -j4" in "cpp/accel/sdsoc_build"
I've met the following error

sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../accel_test_bnn.cpp -o accel_test_bnn.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g

sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../Accel.cpp -o Accel.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g

sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../AccelSchedule.cpp -o AccelSchedule.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g

sds++ -sds-pf zed -dmclkid 1 -sds-hw top Accel.cpp -clkid 1 -hls-tcl sds.tcl -sds-end -c ../AccelTest.cpp -o AccelTest.o -DHLS_COMPILE -I../../utils -O3 -std=gnu++11 -g

Processing -sds-hw block for top
Platform system configuration option -sds-sys-config was not specified, searching for a configuration that uses the specified OS linux

Using system configuration -sds-sys-config linux
child process exited abnormally
while executing
"exec which [apc_get_global APCC_TOOLCHAIN]g++"
(procedure "sdscc_set_toolchain_config" line 27)
invoked from within
"sdscc_set_toolchain_config $toolchain_config $toolchain_type $proc_type $toolchain_name"
(file "/home/wyx/Xilinx/SDx/2017.2/bin/xdcc.tcl" line 3581)

Is it something wrong with the SDSOC?
Thanks!

@rzhao01 I am trying to run yolo on fpgas in a efficient way. I was thinking of maybe I can run binarized yolo on fpga using your work. will I be able to do this ? What changes do I need to make ? If I find a binarized weightsof yolo, then would it be possible ? please guide me.

Thanks in advanced !

PIX_PER_PHASE seems to be important in the accelerator.
And it's 2*32*32 in accel.h.
Could you clarify how the value is determined?