cpldcpu / pcbflow Goto Github PK

Hi Tim, I recalled this awesome project from last year in the ⁠Tiny Tapeout⁠ slack. I couldnt find the run_25_synthesis_wokwi script you used. Was it calling the Wokwi verilog API, download and run the verilog file through the run_20_synthesis?

I want to explore interfacing (and expanding) PCBflow to my own synthesis tool (MRCS) and build tiny tape out sized binary encoded ternary circuits with LTL. I'm not sure which route to explore first, pure NAND/NOR based or custom logic gate logic. The setup cost for us are irrelevant since we would do the PCB manufacturing and PCBA at our lab which are mostly one-offs.

Have you run SPICE simulations of the synthesized PCB's? Any tips/gotchas with this flow are welcome. Cheers! Steven

I slightly modified one of the provided flows to replace the GHDL step with:

read_verilog -sv -formal ../main.sv ../vinclude/*.sv
hierarchy -check -top Mover
proc

but the generated spice will not contain any SUBCKTs, which PCBPlace dies about.
any ideas?

the code at the time of writing this issue is available in this commit, executed from the sim/pcb/ folder with this command: yosys flow_discrete_LTL.ys

Hi,
I tried to use PCBFlow on a VHDL design of mine. In particular, it is a complex adder(my implementation of the Pentium 4 Adder).
After some trial and error I've successfully completed phases 10 (HDL Analysis) and 20 (Synthesis).
The synthesis has been performed with the standard RT logic.
The problem comes in the placement: when I try to launch the bash script for the placement, the PCBPlace.py script return this error:

Exception during parsing of input file '209_synthesized_output.sp'
Conflicting line: '.SUBCKT carryselectblock_4 op1.0 op1.1 op1.2 op1.3 op2.0 op2.1 op2.2 op2.3 cin o.0 o.1 o.2 o.3'
Exception message: Could not insert I/O cell in line zero! Please increase the X-width of the cell array or correct FixedIO assignment.

I've tried digging a bit around but with my limited SPICE knowledge I couldn't figure out a proper solution.
I'm leaving in the attachment the synthesised SPICE and JSON netlists (I changed the extension from .sp and .json to .txt otherwise GitHub wouldn't let me upload it), resulting from Yosys synthesis as I think can be of help.
Please let me know if I can help in some way debugging the code or figuring out where the issue could be.

209_synthesized_output.json.txt
209_synthesized_output.sp.txt