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View Code? Open in Web Editor NEWXilinx PCIe to MIG DDR4 example designs and custom part data files
License: Apache License 2.0
Xilinx PCIe to MIG DDR4 example designs and custom part data files
License: Apache License 2.0
Any email or way to contact you. i have an opportunity to design VCU1525 boards which are high performing low power mining boards and manufacture FPGA PCB Board and then then users can add/install VCU9P, VCU13P chips or any other that fits the socket
Memory on the Board HBM2 or GDDR6 64 GB ( 16 GB x 4 ) or 32 GB ( 8 Gb x 4 ) but remove all other unnecessary parts and only optimize for mining different crypto currencies but also can be chained as a cluster . The Cluster part is very import to be able to cheaply build a chained cluster
Let Me Know regards
jacob
Hi
I received error when doing
source Custom_Part_Data_Files-master/Boards/Xilinx_BCU1525/create_project.tcl
and Error as follows
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:util_ds_buf:2.2
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0"
(file "Custom_Part_Data_Files-master/Boards/Xilinx_BCU1525/create_project.tcl" line 68)
INFO: [Common 17-17] undo 'startgroup'
update_compile_order -fileset sources_1
Any idea on how to fix it ?
Thanks
Thanks for sharing! It works on my BCU1525.
BTW, I cannot find any details about QSFP28 pinouts on BCU1525, is it possible to share this part?
Thanks a lot!
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