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aetherlinghaskellir's Issues

Separate Memory Access From Address Generation

This will allow for:

  1. Separate behavior for scatter/gather, strided, and contiguous write/read.
  2. User-specified math on memory operations
  3. Easier parallelization of memory primitives

The solution for this issue should address the comment #14 (review)

feature requestion

I found one thing that was a little inconvenient about slowDown.

Consider the following:

adder = Add T_Int
adder4 = speedUp 4 adder
adder1 = slowDown 4 adder4

The input type signature of adder and adder1 are not the same

adder : T_Int -> T_Int -> T_Int
adder1 : T_Array 1 T_Int -> T_Array 1 T_Int -> T_Array 1 T_Int

So technically slowdown 4 $ speedup 4 is not the identity. It would be nice if was. However, this would require identification of when map 1 f can be safely replaced with f. However, it's a little nuanced, since consider this case, where f initially begins with a map 1 ...

f = Map 1 (Add T_Int)

f1 = speedup 4 slowDown 4 f

And now f and f1 have the same signature. So speedup 4 slowDown 4 on f is ID, but not on adder.

I suspect the answer is to say that speedup x slowdown x should be the identity if the program is in some canonical form. That form should probably not contain unnecessary map 1 f's.

Questions From Simulator

A running list of questions. I'll add more as I think of them.

Why are the inStrLens Maybe's? It seems like the code is generating a list of stream lengths, wrapping them in Justs, and then unwrapping them.
Wrapping: https://github.com/David-Durst/aetherlingHaskellIR/blob/master/src/Core/Aetherling/Simulator/Simulator.hs#L74
Example of unwrapping:

knownStrLens = filter (/=Nothing) inStrLens

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