Python-based RISC-V Full System Simulator.

Punxa provides HDL models of different parts of a full RISC-V system designed in different design styles using py4hw.

For the processor, we currently support two 64-bit models :

• Behavioral Model of a single-cycle execution processor without pipeline
• Microprogrammed structural design with an algorithmic Control Unit implementation

The single-cycle version suppports full system simulation and proxy-kernel simulation (as in Spike). We also introduce a Linux proxy-kernel to simulate applications compiled with riscv64-unknown-linux-gnu-gcc.

We started focussing on RV64 and Baremetal applications (compiled with risc64-unknown-elf-gcc). When completed, next goal is Linux boot.

RV64 ISA tests progress:

check riscv-tests for a complete list

• Hello World
• Mandelbrot
• File sort
• Paranoia